340 lines
8.9 KiB
C
340 lines
8.9 KiB
C
/*-
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* Copyright 2002 by Peter Grehan. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Mac-io ATA controller
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*/
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/malloc.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <sys/ata.h>
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#include <dev/ata/ata-all.h>
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#include <ata_if.h>
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#include <dev/ofw/ofw_bus.h>
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#include "ata_dbdma.h"
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/*
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* Offset to control registers from base
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*/
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#define ATA_MACIO_ALTOFFSET 0x160
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/*
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* Define the gap between registers
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*/
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#define ATA_MACIO_REGGAP 16
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/*
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* Whether or not to bind to the DBDMA IRQ
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*/
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#define USE_DBDMA_IRQ 0
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/*
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* Timing register
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*/
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#define ATA_MACIO_TIMINGREG 0x200
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#define ATA_TIME_TO_TICK(rev,time) howmany(time, (rev == 4) ? 15 : 30)
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#define PIO_REC_OFFSET 4
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#define PIO_REC_MIN 1
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#define PIO_ACT_MIN 1
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#define DMA_REC_OFFSET 1
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#define DMA_REC_MIN 1
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#define DMA_ACT_MIN 1
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struct ide_timings {
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int cycle; /* minimum cycle time [ns] */
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int active; /* minimum command active time [ns] */
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};
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struct ide_timings pio_timings[5] = {
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{ 600, 180 }, /* PIO 0 */
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{ 390, 150 }, /* PIO 1 */
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{ 240, 105 }, /* PIO 2 */
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{ 180, 90 }, /* PIO 3 */
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{ 120, 75 } /* PIO 4 */
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};
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static const struct ide_timings dma_timings[3] = {
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{ 480, 240 }, /* WDMA 0 */
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{ 165, 90 }, /* WDMA 1 */
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{ 120, 75 } /* WDMA 2 */
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};
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static const struct ide_timings udma_timings[5] = {
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{ 120, 180 }, /* UDMA 0 */
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{ 90, 150 }, /* UDMA 1 */
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{ 60, 120 }, /* UDMA 2 */
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{ 45, 90 }, /* UDMA 3 */
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{ 30, 90 } /* UDMA 4 */
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};
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/*
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* Define the macio ata bus attachment.
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*/
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static int ata_macio_probe(device_t dev);
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static void ata_macio_setmode(device_t parent, device_t dev);
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static int ata_macio_attach(device_t dev);
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static int ata_macio_begin_transaction(struct ata_request *request);
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static device_method_t ata_macio_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ata_macio_probe),
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DEVMETHOD(device_attach, ata_macio_attach),
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/* ATA interface */
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DEVMETHOD(ata_setmode, ata_macio_setmode),
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{ 0, 0 }
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};
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struct ata_macio_softc {
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struct ata_dbdma_channel sc_ch;
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int rev;
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int max_mode;
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struct resource *sc_mem;
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uint32_t udmaconf[2];
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uint32_t wdmaconf[2];
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uint32_t pioconf[2];
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};
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static driver_t ata_macio_driver = {
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"ata",
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ata_macio_methods,
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sizeof(struct ata_macio_softc),
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};
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DRIVER_MODULE(ata, macio, ata_macio_driver, ata_devclass, 0, 0);
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MODULE_DEPEND(ata, ata, 1, 1, 1);
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static int
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ata_macio_probe(device_t dev)
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{
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const char *type = ofw_bus_get_type(dev);
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const char *name = ofw_bus_get_name(dev);
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struct ata_macio_softc *sc;
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struct ata_channel *ch;
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int rid, i;
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if (strcmp(type, "ata") != 0 &&
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strcmp(type, "ide") != 0)
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return (ENXIO);
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sc = device_get_softc(dev);
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bzero(sc, sizeof(struct ata_macio_softc));
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ch = &sc->sc_ch.sc_ch;
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if (strcmp(name,"ata-4") == 0) {
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sc->rev = 4;
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sc->max_mode = ATA_UDMA4;
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} else {
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sc->rev = 3;
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sc->max_mode = ATA_WDMA2;
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}
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rid = 0;
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sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->sc_mem == NULL) {
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device_printf(dev, "could not allocate memory\n");
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return (ENXIO);
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}
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/*
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* Set up the resource vectors
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*/
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for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
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ch->r_io[i].res = sc->sc_mem;
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ch->r_io[i].offset = i * ATA_MACIO_REGGAP;
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}
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ch->r_io[ATA_CONTROL].res = sc->sc_mem;
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ch->r_io[ATA_CONTROL].offset = ATA_MACIO_ALTOFFSET;
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ata_default_registers(dev);
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ch->unit = 0;
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ch->flags |= ATA_USE_16BIT;
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ata_generic_hw(dev);
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return (ata_probe(dev));
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}
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static int
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ata_macio_attach(device_t dev)
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{
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struct ata_macio_softc *sc = device_get_softc(dev);
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uint32_t timingreg;
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#if USE_DBDMA_IRQ
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int dbdma_irq_rid = 1;
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struct resource *dbdma_irq;
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void *cookie;
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#endif
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/* Init DMA engine */
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sc->sc_ch.dbdma_rid = 1;
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sc->sc_ch.dbdma_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->sc_ch.dbdma_rid, RF_ACTIVE);
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ata_dbdma_dmainit(dev);
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/* Configure initial timings */
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timingreg = bus_read_4(sc->sc_mem, ATA_MACIO_TIMINGREG);
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if (sc->rev == 4) {
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sc->udmaconf[0] = sc->udmaconf[1] = timingreg & 0x1ff00000;
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sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0x001ffc00;
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sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000003ff;
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} else {
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sc->udmaconf[0] = sc->udmaconf[1] = 0;
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sc->wdmaconf[0] = sc->wdmaconf[1] = timingreg & 0xfffff800;
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sc->pioconf[0] = sc->pioconf[1] = timingreg & 0x000007ff;
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}
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#if USE_DBDMA_IRQ
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/* Bind to DBDMA interrupt as well */
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if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) {
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bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL,
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(driver_intr_t *)ata_interrupt, sc,&cookie);
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}
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#endif
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/* Set begin_transaction */
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sc->sc_ch.sc_ch.hw.begin_transaction = ata_macio_begin_transaction;
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return ata_attach(dev);
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}
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static void
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ata_macio_setmode(device_t parent, device_t dev)
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{
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struct ata_device *atadev = device_get_softc(dev);
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struct ata_macio_softc *sc = device_get_softc(parent);
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int mode = atadev->mode;
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int min_cycle = 0, min_active = 0;
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int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick;
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mode = ata_limit_mode(dev, mode, sc->max_mode);
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if (ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
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return;
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atadev->mode = mode;
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if ((mode & ATA_DMA_MASK) == ATA_UDMA0) {
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min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle;
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min_active = udma_timings[mode & ATA_MODE_MASK].active;
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cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
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act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
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/* mask: 0x1ff00000 */
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sc->udmaconf[atadev->unit] =
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(cycle_tick << 21) | (act_tick << 25) | 0x100000;
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} else if ((mode & ATA_DMA_MASK) == ATA_WDMA0) {
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min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle;
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min_active = dma_timings[mode & ATA_MODE_MASK].active;
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cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
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act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
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if (sc->rev == 4) {
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inact_tick = cycle_tick - act_tick;
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/* mask: 0x001ffc00 */
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sc->wdmaconf[atadev->unit] =
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(act_tick << 10) | (inact_tick << 15);
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} else {
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inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET;
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if (inact_tick < DMA_REC_MIN)
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inact_tick = DMA_REC_MIN;
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half_tick = 0; /* XXX */
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/* mask: 0xfffff800 */
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sc->wdmaconf[atadev->unit] = (half_tick << 21)
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| (inact_tick << 16) | (act_tick << 11);
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}
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} else {
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min_cycle =
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pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle;
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min_active =
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pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].active;
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cycle_tick = ATA_TIME_TO_TICK(sc->rev,min_cycle);
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act_tick = ATA_TIME_TO_TICK(sc->rev,min_active);
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if (sc->rev == 4) {
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inact_tick = cycle_tick - act_tick;
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/* mask: 0x000003ff */
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sc->pioconf[atadev->unit] =
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(inact_tick << 5) | act_tick;
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} else {
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if (act_tick < PIO_ACT_MIN)
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act_tick = PIO_ACT_MIN;
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inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET;
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if (inact_tick < PIO_REC_MIN)
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inact_tick = PIO_REC_MIN;
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/* mask: 0x000007ff */
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sc->pioconf[atadev->unit] =
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(inact_tick << 5) | act_tick;
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}
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}
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}
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static int
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ata_macio_begin_transaction(struct ata_request *request)
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{
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struct ata_device *atadev = device_get_softc(request->dev);
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struct ata_macio_softc *sc = device_get_softc(request->parent);
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bus_write_4(sc->sc_mem, ATA_MACIO_TIMINGREG,
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sc->udmaconf[atadev->unit] | sc->wdmaconf[atadev->unit]
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| sc->pioconf[atadev->unit]);
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return ata_begin_transaction(request);
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}
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