c350c330da
This lets us run programs containing newer (eg bwx) instructions on older (eg EV5 and less) machines. One win is that we can now run Acrobat4 on EV4s and EV5s. Obtained from: NetBSD Glanced at by: mjacob
700 lines
16 KiB
C
700 lines
16 KiB
C
/* $FreeBSD$ */
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/* $NetBSD: db_instruction.h,v 1.4 1997/09/16 22:53:32 thorpej Exp $ */
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/*
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* Mach Operating System
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* Copyright (c) 1993,1992 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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/*
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* File: alpha_instruction.h
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 11/91
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*
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* Alpha Instruction set definition
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*
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* Reference: "Alpha System Reference Manual", V4.0, April 1991
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*
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*/
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#ifndef _ALPHA_INSTRUCTION_H_
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#define _ALPHA_INSTRUCTION_H_ 1
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#if !defined(ASSEMBLER)
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/*
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* All instructions are in one of five formats:
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* Memory, Branch, Operate, Floating-point Operate, PAL
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*
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* One minor departure from DEC's conventions is we use names
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* for registers that are more akin their software use, e.g.
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* rather then bluntly call them Ra/Rb/Rc we make clear which
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* one is a source (Rs) and which one is a destination (Rd).
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* When a second source register is defined we call it Rt.
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*/
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typedef union {
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/*
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* All instructions are 32 bits wide
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*/
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unsigned int bits;
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/*
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* Generic instruction pseudo format; look at
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* opcode to see how to interpret the rest.
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*/
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struct {
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unsigned bits : 26,
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opcode : 6;
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} generic_format;
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/*
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* Memory instructions contain a 16 bit
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* signed immediate value and two register
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* specifiers
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*/
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struct {
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signed short displacement;
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unsigned rs : 5,
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rd : 5,
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opcode : 6;
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} mem_format;
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/*
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* Branch instruction contain a 21 bit offset,
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* which is sign-extended, shifted and combined
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* with the PC to form a 64 bit destination address.
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*
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* In computed jump instructions the opcode is further
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* specified in the offset field, the rest of it is
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* used as branch target hint. The destination of the
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* jump is the source register.
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*/
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struct {
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signed int displacement : 21;
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unsigned rd : 5,
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opcode : 6;
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} branch_format;
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struct {
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signed int hint : 14;
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unsigned action : 2,
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rs : 5,
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rd : 5,
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opcode : 6;
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} jump_format;
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struct {
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signed int offset : 16;
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unsigned rb : 5;
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unsigned ra : 5;
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unsigned opcode : 6;
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} memory_format;
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/*
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* Operate instructions are of two types, with
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* a second source register or with a literal
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* specifier. Bit 12 sez which is which.
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*/
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struct {
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unsigned rc : 5,
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function : 7,
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is_lit : 1,
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sbz_or_litlo : 3,
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rb_or_lithi : 5,
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ra : 5,
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opcode : 6;
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} operate_generic_format;
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struct {
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unsigned rd : 5,
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function : 7,
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sbz : 4,
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rt : 5,
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rs : 5,
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opcode : 6;
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} operate_reg_format;
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struct {
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unsigned rd : 5,
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function : 7,
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one : 1,
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literal : 8,
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rs : 5,
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opcode : 6;
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} operate_lit_format;
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/*
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* Floating point operate instruction are quite
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* uniform in the encoding. As for the semantics..
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*/
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struct {
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unsigned fd : 5,
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function : 11,
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ft : 5,
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fs : 5,
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opcode : 6;
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} float_format;
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/*
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* PAL instructions just define the major opcode
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*/
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struct {
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unsigned function : 26,
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opcode : 6;
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} pal_format;
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} alpha_instruction;
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#endif !defined(ASSEMBLER)
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/*
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*
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* Encoding of regular instructions (Appendix C op cit)
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*
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*/
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/* OPCODE, bits 26..31 */
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#define op_pal 0x00 /* see PAL sub-table */
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/* 1..7 reserved */
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#define op_lda 0x08
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#define op_ldah 0x09
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#define op_ldbu 0x0a
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#define op_ldq_u 0x0b
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#define op_ldwu 0x0c
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#define op_stw 0x0d
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#define op_stb 0x0e
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#define op_stq_u 0x0f
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#define op_arit 0x10 /* see ARIT sub-table */
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#define op_logical 0x11 /* see LOGICAL sub-table */
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#define op_bit 0x12 /* see BIT sub-table */
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#define op_mul 0x13 /* see MUL sub-table */
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/* reserved */
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#define op_vax_float 0x15 /* see FLOAT sub-table */
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#define op_ieee_float 0x16 /* see FLOAT sub-table */
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#define op_any_float 0x17 /* see FLOAT sub-table */
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#define op_special 0x18 /* see SPECIAL sub-table */
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#define op_pal19 0x19 /* reserved for pal code */
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#define op_j 0x1a /* see JUMP sub-table */
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#define op_pal1b 0x1b /* reserved for pal code */
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#define op_intmisc 0x1c /* see INTMISC sub-table */
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#define op_pal1d 0x1d /* reserved for pal code */
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#define op_pal1e 0x1e /* reserved for pal code */
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#define op_pal1f 0x1f /* reserved for pal code */
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#define op_ldf 0x20
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#define op_ldg 0x21
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#define op_lds 0x22
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#define op_ldt 0x23
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#define op_stf 0x24
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#define op_stg 0x25
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#define op_sts 0x26
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#define op_stt 0x27
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#define op_ldl 0x28
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#define op_ldq 0x29
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#define op_ldl_l 0x2a
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#define op_ldq_l 0x2b
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#define op_stl 0x2c
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#define op_stq 0x2d
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#define op_stl_c 0x2e
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#define op_stq_c 0x2f
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#define op_br 0x30
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#define op_fbeq 0x31
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#define op_fblt 0x32
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#define op_fble 0x33
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#define op_bsr 0x34
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#define op_fbne 0x35
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#define op_fbge 0x36
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#define op_fbgt 0x37
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#define op_blbc 0x38
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#define op_beq 0x39
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#define op_blt 0x3a
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#define op_ble 0x3b
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#define op_blbs 0x3c
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#define op_bne 0x3d
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#define op_bge 0x3e
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#define op_bgt 0x3f
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/* PAL, "function" opcodes (bits 0..25) */
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/*
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* What we will implement is TBD. These are the unprivileged ones
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* that we probably have to support for compat reasons.
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*/
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/* See <machine/pal.h> */
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/* ARIT, "function" opcodes (bits 5..11) */
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#define op_addl 0x00
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#define op_s4addl 0x02
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#define op_subl 0x09
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#define op_s4subl 0x0b
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#define op_cmpbge 0x0f
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#define op_s8addl 0x12
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#define op_s8subl 0x1b
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#define op_cmpult 0x1d
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#define op_addq 0x20
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#define op_s4addq 0x22
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#define op_subq 0x29
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#define op_s4subq 0x2b
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#define op_cmpeq 0x2d
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#define op_s8addq 0x32
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#define op_s8subq 0x3b
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#define op_cmpule 0x3d
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#define op_addl_v 0x40
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#define op_subl_v 0x49
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#define op_cmplt 0x4d
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#define op_addq_v 0x60
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#define op_subq_v 0x69
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#define op_cmple 0x6d
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/* LOGICAL, "function" opcodes (bits 5..11) */
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#define op_and 0x00
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#define op_andnot 0x08 /* bic */
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#define op_cmovlbs 0x14
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#define op_cmovlbc 0x16
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#define op_or 0x20 /* bis */
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#define op_cmoveq 0x24
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#define op_cmovne 0x26
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#define op_ornot 0x28
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#define op_xor 0x40
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#define op_cmovlt 0x44
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#define op_cmovge 0x46
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#define op_xornot 0x48 /* eqv */
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#define op_amask 0x61
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#define op_cmovle 0x64
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#define op_cmovgt 0x66
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#define op_implver 0x6c
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/* BIT, "function" opcodes (bits 5..11) */
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#define op_mskbl 0x02
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#define op_extbl 0x06
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#define op_insbl 0x0b
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#define op_mskwl 0x12
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#define op_extwl 0x16
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#define op_inswl 0x1b
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#define op_mskll 0x22
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#define op_extll 0x26
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#define op_insll 0x2b
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#define op_zap 0x30
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#define op_zapnot 0x31
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#define op_mskql 0x32
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#define op_srl 0x34
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#define op_extql 0x36
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#define op_sll 0x39
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#define op_insql 0x3b
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#define op_sra 0x3c
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#define op_mskwh 0x52
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#define op_inswh 0x57
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#define op_extwh 0x5a
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#define op_msklh 0x62
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#define op_inslh 0x67
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#define op_extlh 0x6a
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#define op_extqh 0x7a
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#define op_insqh 0x77
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#define op_mskqh 0x72
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/* MUL, "function" opcodes (bits 5..11) */
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#define op_mull 0x00
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#define op_mulq_v 0x60
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#define op_mull_v 0x40
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#define op_umulh 0x30
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#define op_mulq 0x20
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/* SPECIAL, "displacement" opcodes (bits 0..15) */
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#define op_draint 0x0000
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#define op_mb 0x4000
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#define op_fetch 0x8000
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#define op_fetch_m 0xa000
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#define op_rpcc 0xc000
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#define op_rc 0xe000
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#define op_rs 0xf000
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/* JUMP, "action" opcodes (bits 14..15) */
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#define op_jmp 0x0
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#define op_jsr 0x1
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#define op_ret 0x2
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#define op_jcr 0x3
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/* INTMISC, "function" opcodes (operate format) */
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#define op_sextb 0x00
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#define op_sextw 0x01
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#define op_ctpop 0x30
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#define op_perr 0x31
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#define op_ctlz 0x32
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#define op_cttz 0x33
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#define op_unpkbw 0x34
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#define op_unpkbl 0x35
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#define op_pkwb 0x36
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#define op_pklb 0x37
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#define op_minsb8 0x38
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#define op_minsw4 0x39
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#define op_minub8 0x3a
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#define op_minuw4 0x3b
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#define op_maxub8 0x3c
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#define op_maxuw4 0x3d
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#define op_maxsb8 0x3e
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#define op_maxsw4 0x3f
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#define op_ftoit 0x70
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#define op_ftois 0x78
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/*
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*
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* Encoding of floating point instructions (pagg. C-5..6 op cit)
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*
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* Load and store operations use opcodes op_ldf..op_stt
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*/
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/* any FLOAT, "function" opcodes (bits 5..11) */
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#define op_cvtlq 0x010
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#define op_cpys 0x020
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#define op_cpysn 0x021
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#define op_cpyse 0x022
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#define op_mt_fpcr 0x024
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#define op_mf_fpcr 0x025
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#define op_fcmoveq 0x02a
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#define op_fcmovne 0x02b
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#define op_fcmovlt 0x02c
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#define op_fcmovge 0x02d
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#define op_fcmovle 0x02e
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#define op_fcmovgt 0x02f
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#define op_cvtql 0x030
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#define op_cvtql_v 0x130
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#define op_cvtql_sv 0x330
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/* ieee FLOAT, "function" opcodes (bits 5..11) */
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#define op_adds_c 0x000
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#define op_subs_c 0x001
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#define op_muls_c 0x002
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#define op_divs_c 0x003
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#define op_addt_c 0x020
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#define op_subt_c 0x021
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#define op_mult_c 0x022
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#define op_divt_c 0x023
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#define op_cvtts_c 0x02c
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#define op_cvttq_c 0x02f
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#define op_cvtqs_c 0x03c
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#define op_cvtqt_c 0x03e
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#define op_adds_m 0x040
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#define op_subs_m 0x041
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#define op_muls_m 0x042
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#define op_divs_m 0x043
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#define op_addt_m 0x060
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#define op_subt_m 0x061
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#define op_mult_m 0x062
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#define op_divt_m 0x063
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#define op_cvtts_m 0x06c
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#define op_cvtqs_m 0x07c
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#define op_cvtqt_m 0x07e
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#define op_adds 0x080
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#define op_subs 0x081
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#define op_muls 0x082
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#define op_divs 0x083
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#define op_addt 0x0a0
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#define op_subt 0x0a1
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#define op_mult 0x0a2
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#define op_divt 0x0a3
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#define op_cmptun 0x0a4
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#define op_cmpteq 0x0a5
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#define op_cmptlt 0x0a6
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#define op_cmptle 0x0a7
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#define op_cvtts 0x0ac
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#define op_cvttq 0x0af
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#define op_cvtqs 0x0bc
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#define op_cvtqt 0x0be
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#define op_adds_d 0x0c0
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#define op_subs_d 0x0c1
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#define op_muls_d 0x0c2
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#define op_divs_d 0x0c3
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#define op_addt_d 0x0e0
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#define op_subt_d 0x0e1
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#define op_mult_d 0x0e2
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#define op_divt_d 0x0e3
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#define op_cvtts_d 0x0ec
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#define op_cvtqs_d 0x0fc
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#define op_cvtqt_d 0x0fe
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#define op_adds_uc 0x100
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#define op_subs_uc 0x101
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#define op_muls_uc 0x102
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#define op_divs_uc 0x103
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#define op_addt_uc 0x120
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#define op_subt_uc 0x121
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#define op_mult_uc 0x122
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#define op_divt_uc 0x123
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#define op_cvtts_uc 0x12c
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#define op_cvttq_vc 0x12f
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#define op_adds_um 0x140
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#define op_subs_um 0x141
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#define op_muls_um 0x142
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#define op_divs_um 0x143
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#define op_addt_um 0x160
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#define op_subt_um 0x161
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#define op_mult_um 0x162
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#define op_divt_um 0x163
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#define op_cvtts_um 0x16c
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#define op_adds_u 0x180
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#define op_subs_u 0x181
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#define op_muls_u 0x182
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#define op_divs_u 0x183
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#define op_addt_u 0x1a0
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#define op_subt_u 0x1a1
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#define op_mult_u 0x1a2
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#define op_divt_u 0x1a3
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#define op_cvtts_u 0x1ac
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#define op_cvttq_v 0x1af
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#define op_adds_ud 0x1c0
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#define op_subs_ud 0x1c1
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#define op_muls_ud 0x1c2
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#define op_divs_ud 0x1c3
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#define op_addt_ud 0x1e0
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#define op_subt_ud 0x1e1
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#define op_mult_ud 0x1e2
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#define op_divt_ud 0x1e3
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#define op_cvtts_ud 0x1ec
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#define op_adds_suc 0x500
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#define op_subs_suc 0x501
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#define op_muls_suc 0x502
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#define op_divs_suc 0x503
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#define op_addt_suc 0x520
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#define op_subt_suc 0x521
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#define op_mult_suc 0x522
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#define op_divt_suc 0x523
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#define op_cvtts_suc 0x52c
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#define op_cvttq_svc 0x52f
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#define op_adds_sum 0x540
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#define op_subs_sum 0x541
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#define op_muls_sum 0x542
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#define op_divs_sum 0x543
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#define op_addt_sum 0x560
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#define op_subt_sum 0x561
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#define op_mult_sum 0x562
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#define op_divt_sum 0x563
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#define op_cvtts_sum 0x56c
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#define op_adds_su 0x580
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#define op_subs_su 0x581
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#define op_muls_su 0x582
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#define op_divs_su 0x583
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#define op_addt_su 0x5a0
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#define op_subt_su 0x5a1
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#define op_mult_su 0x5a2
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#define op_divt_su 0x5a3
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#define op_cmptun_su 0x5a4
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#define op_cmpteq_su 0x5a5
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#define op_cmptlt_su 0x5a6
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#define op_cmptle_su 0x5a7
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#define op_cvtts_su 0x5ac
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#define op_cvttq_sv 0x5af
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#define op_adds_sud 0x5c0
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#define op_subs_sud 0x5c1
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#define op_muls_sud 0x5c2
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#define op_divs_sud 0x5c3
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#define op_addt_sud 0x5e0
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#define op_subt_sud 0x5e1
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#define op_mult_sud 0x5e2
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#define op_divt_sud 0x5e3
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#define op_cvtts_sud 0x5ec
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#define op_adds_suic 0x700
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#define op_subs_suic 0x701
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#define op_muls_suic 0x702
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#define op_divs_suic 0x703
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#define op_addt_suic 0x720
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#define op_subt_suic 0x721
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#define op_mult_suic 0x722
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#define op_divt_suic 0x723
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#define op_cvtts_suic 0x72c
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#define op_cvttq_svic 0x72f
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#define op_cvtqs_suic 0x73c
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#define op_cvtqt_suic 0x73e
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#define op_adds_suim 0x740
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#define op_subs_suim 0x741
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#define op_muls_suim 0x742
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#define op_divs_suim 0x743
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#define op_addt_suim 0x760
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#define op_subt_suim 0x761
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#define op_mult_suim 0x762
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#define op_divt_suim 0x763
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#define op_cvtts_suim 0x76c
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#define op_cvtqs_suim 0x77c
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#define op_cvtqt_suim 0x77e
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#define op_adds_sui 0x780
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#define op_subs_sui 0x781
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#define op_muls_sui 0x782
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#define op_divs_sui 0x783
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#define op_addt_sui 0x7a0
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#define op_subt_sui 0x7a1
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#define op_mult_sui 0x7a2
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#define op_divt_sui 0x7a3
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#define op_cvtts_sui 0x7ac
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#define op_cvttq_svi 0x7af
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#define op_cvtqs_sui 0x7bc
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#define op_cvtqt_sui 0x7be
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#define op_adds_suid 0x7c0
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#define op_subs_suid 0x7c1
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#define op_muls_suid 0x7c2
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#define op_divs_suid 0x7c3
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#define op_addt_suid 0x7e0
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#define op_subt_suid 0x7e1
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#define op_mult_suid 0x7e2
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#define op_divt_suid 0x7e3
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#define op_cvtts_suid 0x7ec
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#define op_cvtqs_suid 0x7fc
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#define op_cvtqt_suid 0x7fe
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/* vax FLOAT, "function" opcodes (bits 5..11) */
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#define op_addf_c 0x000
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#define op_subf_c 0x001
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#define op_mulf_c 0x002
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#define op_divf_c 0x003
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#define op_cvtdg_c 0x01e
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#define op_addg_c 0x020
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#define op_subg_c 0x021
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#define op_mulg_c 0x022
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#define op_divg_c 0x023
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#define op_cvtgf_c 0x02c
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#define op_cvtgd_c 0x02d
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#define op_cvtgqg_c 0x02f
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#define op_cvtqf_c 0x03c
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#define op_cvtqg_c 0x03e
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#define op_addf 0x080
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#define op_subf 0x081
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#define op_mulf 0x082
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#define op_divf 0x083
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#define op_cvtdg 0x09e
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#define op_addg 0x0a0
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#define op_subg 0x0a1
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#define op_mulg 0x0a2
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#define op_divg 0x0a3
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#define op_cmpgeq 0x0a5
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#define op_cmpglt 0x0a6
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#define op_cmpgle 0x0a7
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#define op_cvtgf 0x0ac
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#define op_cvtgd 0x0ad
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#define op_cvtgq 0x0af
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#define op_cvtqf 0x0bc
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#define op_cvtqg 0x0be
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#define op_addf_uc 0x100
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#define op_subf_uc 0x101
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#define op_mulf_uc 0x102
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#define op_divf_uc 0x103
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#define op_cvtdg_uc 0x11e
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#define op_addg_uc 0x120
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#define op_subg_uc 0x121
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#define op_mulg_uc 0x122
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#define op_divg_uc 0x123
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#define op_cvtgf_uc 0x12c
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#define op_cvtgd_uc 0x12d
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#define op_cvtgqg_vc 0x12f
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#define op_addf_u 0x180
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#define op_subf_u 0x181
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#define op_mulf_u 0x182
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#define op_divf_u 0x183
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#define op_cvtdg_u 0x19e
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#define op_addg_u 0x1a0
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#define op_subg_u 0x1a1
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#define op_mulg_u 0x1a2
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#define op_divg_u 0x1a3
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#define op_cvtgf_u 0x1ac
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#define op_cvtgd_u 0x1ad
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#define op_cvtgqg_v 0x1af
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#define op_addf_sc 0x400
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#define op_subf_sc 0x401
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#define op_mulf_sc 0x402
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#define op_divf_sc 0x403
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#define op_cvtdg_sc 0x41e
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#define op_addg_sc 0x420
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#define op_subg_sc 0x421
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#define op_mulg_sc 0x422
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#define op_divg_sc 0x423
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#define op_cvtgf_sc 0x42c
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#define op_cvtgd_sc 0x42d
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#define op_cvtgqg_sc 0x42f
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#define op_cvtqf_sc 0x43c
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#define op_cvtqg_sc 0x43e
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#define op_addf_s 0x480
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#define op_subf_s 0x481
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#define op_mulf_s 0x482
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#define op_divf_s 0x483
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#define op_cvtdg_s 0x49e
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#define op_addg_s 0x4a0
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#define op_subg_s 0x4a1
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#define op_mulg_s 0x4a2
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#define op_divg_s 0x4a3
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#define op_cmpgeq_s 0x4a5
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#define op_cmpglt_s 0x4a6
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#define op_cmpgle_s 0x4a7
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#define op_cvtgf_s 0x4ac
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#define op_cvtgd_s 0x4ad
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#define op_cvtgqg_s 0x4af
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#define op_cvtqf_s 0x4bc
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#define op_cvtqg_s 0x4be
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#define op_addf_suc 0x500
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#define op_subf_suc 0x501
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#define op_mulf_suc 0x502
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#define op_divf_suc 0x503
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#define op_cvtdg_suc 0x51e
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#define op_addg_suc 0x520
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#define op_subg_suc 0x521
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#define op_mulg_suc 0x522
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#define op_divg_suc 0x523
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#define op_cvtgf_suc 0x52c
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#define op_cvtgd_suc 0x52d
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#define op_cvtgqg_svc 0x52f
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#define op_addf_su 0x580
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#define op_subf_su 0x581
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#define op_mulf_su 0x582
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#define op_divf_su 0x583
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#define op_cvtdg_su 0x59e
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#define op_addg_su 0x5a0
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#define op_subg_su 0x5a1
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#define op_mulg_su 0x5a2
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#define op_divg_su 0x5a3
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#define op_cvtgf_su 0x5ac
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#define op_cvtgd_su 0x5ad
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#define op_cvtgqg_sv 0x5af
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#endif /* _ALPHA_INSTRUCTION_H_ */
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