8c9ca28b31
Hide unused code under #ifdef notyet (in one case the only caller is under that same ifdef), or if it is arm (not arm64) specific code under the __arm__ ifdef to not yield -Wunused-function warnings during the arm64 kernel compile. MFC after: 2 weeks
481 lines
12 KiB
C
481 lines
12 KiB
C
/*-
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* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/machdep.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#if defined(__aarch64__)
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#include "opt_soc.h"
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#else
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#include <arm/allwinner/aw_machdep.h>
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#endif
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/**
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* Timer registers addr
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*
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*/
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#define TIMER_IRQ_EN_REG 0x00
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#define TIMER_IRQ_ENABLE(x) (1 << x)
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#define TIMER_IRQ_STA_REG 0x04
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#define TIMER_IRQ_PENDING(x) (1 << x)
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/*
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* On A10, A13, A20 and A31/A31s 6 timers are available
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*/
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#define TIMER_CTRL_REG(x) (0x10 + 0x10 * x)
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#define TIMER_CTRL_START (1 << 0)
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#define TIMER_CTRL_AUTORELOAD (1 << 1)
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#define TIMER_CTRL_CLKSRC_MASK (3 << 2)
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#define TIMER_CTRL_OSC24M (1 << 2)
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#define TIMER_CTRL_PRESCALAR_MASK (0x7 << 4)
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#define TIMER_CTRL_PRESCALAR(x) ((x - 1) << 4)
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#define TIMER_CTRL_MODE_MASK (1 << 7)
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#define TIMER_CTRL_MODE_SINGLE (1 << 7)
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#define TIMER_CTRL_MODE_CONTINUOUS (0 << 7)
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#define TIMER_INTV_REG(x) (0x14 + 0x10 * x)
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#define TIMER_CURV_REG(x) (0x18 + 0x10 * x)
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/* 64 bit counter, available in A10 and A13 */
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#define CNT64_CTRL_REG 0xa0
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#define CNT64_CTRL_RL_EN 0x02 /* read latch enable */
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#define CNT64_LO_REG 0xa4
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#define CNT64_HI_REG 0xa8
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#define SYS_TIMER_CLKSRC 24000000 /* clock source */
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enum a10_timer_type {
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A10_TIMER = 1,
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A23_TIMER,
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};
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struct a10_timer_softc {
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device_t sc_dev;
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struct resource *res[2];
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void *sc_ih; /* interrupt handler */
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uint32_t sc_period;
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uint64_t timer0_freq;
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struct eventtimer et;
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enum a10_timer_type type;
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};
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#define timer_read_4(sc, reg) \
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bus_read_4(sc->res[A10_TIMER_MEMRES], reg)
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#define timer_write_4(sc, reg, val) \
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bus_write_4(sc->res[A10_TIMER_MEMRES], reg, val)
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static u_int a10_timer_get_timecount(struct timecounter *);
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#if defined(__arm__)
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static int a10_timer_timer_start(struct eventtimer *,
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sbintime_t first, sbintime_t period);
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static int a10_timer_timer_stop(struct eventtimer *);
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#endif
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static uint64_t timer_read_counter64(struct a10_timer_softc *sc);
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#if defined(__arm__)
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static void a10_timer_eventtimer_setup(struct a10_timer_softc *sc);
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#endif
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static void a23_timer_timecounter_setup(struct a10_timer_softc *sc);
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static u_int a23_timer_get_timecount(struct timecounter *tc);
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static int a10_timer_irq(void *);
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static int a10_timer_probe(device_t);
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static int a10_timer_attach(device_t);
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#if defined(__arm__)
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static delay_func a10_timer_delay;
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#endif
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static struct timecounter a10_timer_timecounter = {
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.tc_name = "a10_timer timer0",
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.tc_get_timecount = a10_timer_get_timecount,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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.tc_quality = 1000,
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};
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static struct timecounter a23_timer_timecounter = {
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.tc_name = "a10_timer timer0",
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.tc_get_timecount = a23_timer_get_timecount,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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/* We want it to be selected over the arm generic timecounter */
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.tc_quality = 2000,
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};
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#define A10_TIMER_MEMRES 0
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#define A10_TIMER_IRQRES 1
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static struct resource_spec a10_timer_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct ofw_compat_data compat_data[] = {
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{"allwinner,sun4i-a10-timer", A10_TIMER},
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{"allwinner,sun8i-a23-timer", A23_TIMER},
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{NULL, 0},
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};
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static int
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a10_timer_probe(device_t dev)
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{
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struct a10_timer_softc *sc;
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#if defined(__arm__)
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u_int soc_family;
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#endif
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sc = device_get_softc(dev);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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#if defined(__arm__)
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/* For SoC >= A10 we have the ARM Timecounter/Eventtimer */
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soc_family = allwinner_soc_family();
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if (soc_family != ALLWINNERSOC_SUN4I &&
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soc_family != ALLWINNERSOC_SUN5I)
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return (ENXIO);
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#endif
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device_set_desc(dev, "Allwinner timer");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a10_timer_attach(device_t dev)
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{
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struct a10_timer_softc *sc;
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clk_t clk;
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int err;
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sc = device_get_softc(dev);
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sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->sc_dev = dev;
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/* Setup and enable the timer interrupt */
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err = bus_setup_intr(dev, sc->res[A10_TIMER_IRQRES], INTR_TYPE_CLK,
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a10_timer_irq, NULL, sc, &sc->sc_ih);
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if (err != 0) {
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bus_release_resources(dev, a10_timer_spec, sc->res);
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device_printf(dev, "Unable to setup the clock irq handler, "
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"err = %d\n", err);
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return (ENXIO);
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}
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if (clk_get_by_ofw_index(dev, 0, 0, &clk) != 0)
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sc->timer0_freq = SYS_TIMER_CLKSRC;
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else {
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if (clk_get_freq(clk, &sc->timer0_freq) != 0) {
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device_printf(dev, "Cannot get clock source frequency\n");
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return (ENXIO);
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}
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}
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#if defined(__arm__)
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a10_timer_eventtimer_setup(sc);
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arm_set_delay(a10_timer_delay, sc);
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a10_timer_timecounter.tc_priv = sc;
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a10_timer_timecounter.tc_frequency = sc->timer0_freq;
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tc_init(&a10_timer_timecounter);
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#elif defined(__aarch64__)
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a23_timer_timecounter_setup(sc);
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#endif
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if (bootverbose) {
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device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
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device_printf(sc->sc_dev, "event timer clock frequency %ju\n",
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sc->timer0_freq);
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device_printf(sc->sc_dev, "timecounter clock frequency %jd\n",
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a10_timer_timecounter.tc_frequency);
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}
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return (0);
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}
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static int
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a10_timer_irq(void *arg)
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{
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struct a10_timer_softc *sc;
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uint32_t val;
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sc = (struct a10_timer_softc *)arg;
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/* Clear interrupt pending bit. */
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timer_write_4(sc, TIMER_IRQ_STA_REG, TIMER_IRQ_PENDING(0));
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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/*
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* Disabled autoreload and sc_period > 0 means
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* timer_start was called with non NULL first value.
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* Now we will set periodic timer with the given period
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* value.
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*/
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if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
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/* Update timer */
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timer_write_4(sc, TIMER_CURV_REG(0), sc->sc_period);
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/* Make periodic and enable */
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val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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}
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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/*
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* Event timer function for A10 and A13
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*/
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#if defined(__arm__)
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static void
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a10_timer_eventtimer_setup(struct a10_timer_softc *sc)
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{
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uint32_t val;
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/* Set clock source to OSC24M, 1 pre-division, continuous mode */
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
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val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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/* Enable timer0 */
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val = timer_read_4(sc, TIMER_IRQ_EN_REG);
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val |= TIMER_IRQ_ENABLE(0);
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timer_write_4(sc, TIMER_IRQ_EN_REG, val);
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/* Set desired frequency in event timer and timecounter */
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sc->et.et_frequency = sc->timer0_freq;
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sc->et.et_name = "a10_timer Eventtimer";
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sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
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sc->et.et_quality = 1000;
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sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
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sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = a10_timer_timer_start;
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sc->et.et_stop = a10_timer_timer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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}
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static int
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a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
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sbintime_t period)
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{
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struct a10_timer_softc *sc;
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uint32_t count;
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uint32_t val;
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sc = (struct a10_timer_softc *)et->et_priv;
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if (period != 0)
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sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
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else
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sc->sc_period = 0;
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if (first != 0)
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count = ((uint32_t)et->et_frequency * first) >> 32;
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else
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count = sc->sc_period;
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/* Update timer values */
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timer_write_4(sc, TIMER_INTV_REG(0), sc->sc_period);
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timer_write_4(sc, TIMER_CURV_REG(0), count);
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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if (period != 0) {
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/* periodic */
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val |= TIMER_CTRL_AUTORELOAD;
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} else {
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/* oneshot */
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val &= ~TIMER_CTRL_AUTORELOAD;
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}
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/* Enable timer0 */
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val |= TIMER_IRQ_ENABLE(0);
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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return (0);
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}
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static int
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a10_timer_timer_stop(struct eventtimer *et)
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{
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struct a10_timer_softc *sc;
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uint32_t val;
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sc = (struct a10_timer_softc *)et->et_priv;
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/* Disable timer0 */
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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val &= ~TIMER_CTRL_START;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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sc->sc_period = 0;
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return (0);
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}
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#endif
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/*
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* Timecounter functions for A23 and above
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*/
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static void
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a23_timer_timecounter_setup(struct a10_timer_softc *sc)
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{
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uint32_t val;
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/* Set clock source to OSC24M, 1 pre-division, continuous mode */
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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val &= ~TIMER_CTRL_PRESCALAR_MASK | ~TIMER_CTRL_MODE_MASK | ~TIMER_CTRL_CLKSRC_MASK;
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val |= TIMER_CTRL_PRESCALAR(1) | TIMER_CTRL_OSC24M;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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/* Set reload value */
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timer_write_4(sc, TIMER_INTV_REG(0), ~0);
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val = timer_read_4(sc, TIMER_INTV_REG(0));
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/* Enable timer0 */
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val = timer_read_4(sc, TIMER_CTRL_REG(0));
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val |= TIMER_CTRL_AUTORELOAD | TIMER_CTRL_START;
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timer_write_4(sc, TIMER_CTRL_REG(0), val);
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val = timer_read_4(sc, TIMER_CURV_REG(0));
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a23_timer_timecounter.tc_priv = sc;
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a23_timer_timecounter.tc_frequency = sc->timer0_freq;
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tc_init(&a23_timer_timecounter);
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}
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static u_int
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a23_timer_get_timecount(struct timecounter *tc)
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{
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struct a10_timer_softc *sc;
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uint32_t val;
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sc = (struct a10_timer_softc *)tc->tc_priv;
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if (sc == NULL)
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return (0);
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val = timer_read_4(sc, TIMER_CURV_REG(0));
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/* Counter count backwards */
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return (~0u - val);
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}
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/*
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* Timecounter functions for A10 and A13, using the 64 bits counter
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*/
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static uint64_t
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timer_read_counter64(struct a10_timer_softc *sc)
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{
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uint32_t lo, hi;
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/* Latch counter, wait for it to be ready to read. */
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timer_write_4(sc, CNT64_CTRL_REG, CNT64_CTRL_RL_EN);
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while (timer_read_4(sc, CNT64_CTRL_REG) & CNT64_CTRL_RL_EN)
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continue;
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hi = timer_read_4(sc, CNT64_HI_REG);
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lo = timer_read_4(sc, CNT64_LO_REG);
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return (((uint64_t)hi << 32) | lo);
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}
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#if defined(__arm__)
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static void
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a10_timer_delay(int usec, void *arg)
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{
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struct a10_timer_softc *sc = arg;
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uint64_t end, now;
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now = timer_read_counter64(sc);
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end = now + (sc->timer0_freq / 1000000) * (usec + 1);
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while (now < end)
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now = timer_read_counter64(sc);
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}
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#endif
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static u_int
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a10_timer_get_timecount(struct timecounter *tc)
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{
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if (tc->tc_priv == NULL)
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return (0);
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return ((u_int)timer_read_counter64(tc->tc_priv));
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}
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static device_method_t a10_timer_methods[] = {
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DEVMETHOD(device_probe, a10_timer_probe),
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DEVMETHOD(device_attach, a10_timer_attach),
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DEVMETHOD_END
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};
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static driver_t a10_timer_driver = {
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"a10_timer",
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a10_timer_methods,
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sizeof(struct a10_timer_softc),
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};
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static devclass_t a10_timer_devclass;
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EARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0,
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BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
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