d3514c2942
This code implements the "kpssv2" flavour of CPU regulator/clock gating in Linux. It's used by at least the ipq4018/4019 to power on and off CPU cores. This is based on the Linux implementation - the register definitions and values are from Linux and I've reverse engineered the sequencing requirements. The MP bring-up is: * set cold boot address via an SCM call - this is the address used by the bootloader/TZ firmware to jump to when the CPUs boot * power down the LDO feeding the CPU core and wait for it to settle * program in the right set of LDO and power tree configuration for the CPU regulator to power up the core. Unfortunately these are magic numbers that I've not found documented anywhere. * (I think) power up the shared L2 cache connect if it isn't. * Clamp the power into the core down; put the core into reset * Unclamp the power rail; release reset; and then set the core to boot. The MP core will then boot the bootloader/TZ firmware and then will wait until an incoming interrupt kicks it to start @ mpentry. Tested: * IPQ4019, 4 CPUs Release APs CPU(3) applied BP hardening: not necessary CPU(1) applied BP hardening: not necessary CPU(2) applied BP hardening: not necessary Reviewed by: andrew, manu, imp Differential Revision: https://reviews.freebsd.org/D32723
117 lines
3.3 KiB
C
117 lines
3.3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/reboot.h>
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#include <sys/devmap.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/machdep.h>
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#include <machine/platformvar.h>
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#include <machine/smp.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_cpu.h>
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#include <arm/qualcomm/ipq4018_machdep.h>
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#include <arm/qualcomm/qcom_scm_legacy.h>
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#include <arm/qualcomm/qcom_cpu_kpssv2.h>
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#include "platform_if.h"
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void
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ipq4018_mp_setmaxid(platform_t plat)
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{
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int ncpu;
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/* If we've already set the global vars don't bother to do it again. */
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if (mp_ncpus != 0)
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return;
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/* Read current CP15 Cache Size ID Register */
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ncpu = cp15_l2ctlr_get();
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ncpu = CPUV7_L2CTLR_NPROC(ncpu);
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mp_ncpus = ncpu;
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mp_maxid = ncpu - 1;
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printf("SMP: ncpu=%d\n", ncpu);
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}
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static boolean_t
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ipq4018_start_ap(u_int id, phandle_t node, u_int addr_cells, pcell_t *arg)
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{
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/*
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* For the IPQ401x we assume the enable method is
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* "qcom,kpss-acc-v2". If this path gets turned into
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* something more generic for other 32 bit qualcomm
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* SoCs then we'll likely want to turn this into a
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* switch based on "enable-method".
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*/
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return qcom_cpu_kpssv2_regulator_start(id, node);
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}
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void
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ipq4018_mp_start_ap(platform_t plat)
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{
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int ret;
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/*
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* First step - SCM call to set the cold boot address to mpentry, so
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* CPUs hopefully start in the MP path.
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*/
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ret = qcom_scm_legacy_mp_set_cold_boot_address((vm_offset_t) mpentry);
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if (ret != 0)
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panic("%s: Couldn't set cold boot address via SCM "
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"(error 0x%08x)", __func__, ret);
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/*
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* Next step - loop over the CPU nodes and do the per-CPU setup
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* required to power on the CPUs themselves.
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*/
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ofw_cpu_early_foreach(ipq4018_start_ap, true);
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/*
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* The next set of IPIs to the CPUs will wake them up and enter
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* mpentry.
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*/
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}
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