897cd717a5
work in progress and has never booted a real machine. Initial development and testing was done using SimOS (see http://simos.stanford.edu for details). On the SimOS simulator, this port successfully reaches single-user mode and has been tested with loads as high as one copy of /bin/ls :-). Obtained from: partly from NetBSD/alpha
319 lines
12 KiB
C
319 lines
12 KiB
C
/* $NetBSD: tlsbreg.h,v 1.3 1997/04/06 20:08:40 cgd Exp $ */
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/*
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* Copyright (c) 1997 by Matthew Jacob
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* NASA AMES Research Center.
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* All rights reserved.
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*
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* Based in part upon a prototype version by Jason Thorpe
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* Copyright (c) 1996 by Jason Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Definitions for the TurboLaser System Bus found on
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* AlphaServer 8200/8400 systems.
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*/
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/*
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* There are 9 TurboLaser nodes, 0 though 8. Their uses are defined as
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* follows:
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*
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* Node Module
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* ---- ------
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* 0 CPU, Memory
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* 1 CPU, Memory
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* 2 CPU, Memory
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* 3 CPU, Memory
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* 4 CPU, Memory, I/O
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* 5 CPU, Memory, I/O
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* 6 CPU, Memory, I/O
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* 7 CPU, Memory, I/O
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* 8 I/O
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*
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* A node occurs every 0x00400000 bytes.
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*
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* Note, the AlphaServer 8200 only has nodes 4 though 8.
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*/
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#define TLSB_NODE_BASE 0x000000ff88000000 /* Dense */
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#define TLSB_NODE_SIZE 0x00400000
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#define TLSB_NODE_MAX 8
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/* Translate a node number to an address. */
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#define TLSB_NODE_ADDR(_node) \
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(long)(TLSB_NODE_BASE + ((_node) * TLSB_NODE_SIZE))
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#define TLSB_NODE_REG_ADDR(_node, _reg) \
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KV((long)TLSB_NODE_ADDR((_node)) + (_reg))
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/* Access the specified register on the specified node. */
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#define TLSB_GET_NODEREG(_node, _reg) \
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*(volatile u_int32_t *)(TLSB_NODE_REG_ADDR((_node), (_reg)))
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#define TLSB_PUT_NODEREG(_node, _reg, _val) \
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*(volatile u_int32_t *)(TLSB_NODE_REG_ADDR((_node), (_reg))) = (_val)
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/*
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* Some registers are shared by all TurboLaser nodes, and appear in
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* the TurboLaser Broadcast space.
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*/
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#define TLSB_BCAST_BASE 0x000000ff8e000000 /* Dense */
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#define TLSB_BCAST_REG_ADDR(_reg) KV((long)(TLSB_BCASE_BASE + (_reg)))
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/* Access the specified register in the broadcast space. */
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#define TLSB_GET_BCASTREG(_reg) \
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*(volatile u_int32_t *)(TLSB_BCAST_REG_ADDR + (_reg))
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#define TLSB_PUT_BCASTREG(_reg, _val) \
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*(volatile u_int32_t *)(TLSB_BCAST_REG_ADDR + (_reg)) = (_val)
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/*
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* Location of the Gbus, the per-CPU bus containing the clock and
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* console hardware.
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*/
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#define TLSB_GBUS_BASE 0x000000ff90000000 /* Dense */
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/*
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* Note that not every module type supports each TurboLaser register.
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* The following defines the keys used to denote module support for
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* a given register:
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*
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* C Supported by CPU module
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* M Supported by Memory module
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* I Supported by I/O module
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*/
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/*
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* Per-node TurboLaser System Bus registers, offsets from the
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* base of the node.
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*/
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#define TLDEV 0x0000 /* CMI: Device Register */
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#define TLBER 0x0040 /* CMI: Bus Error Register */
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#define TLCNR 0x0080 /* CMI: Congfiguration Register */
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#define TLVID 0x00c0 /* CM: Virtual ID Register */
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#define TLMMR0 0x0200 /* CM: Memory Mapping Register 0 */
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#define TLMMR1 0x0240 /* CM: Memory Mapping Register 1 */
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#define TLMMR2 0x0280 /* CM: Memory Mapping Register 2 */
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#define TLMMR3 0x02c0 /* CM: Memory Mapping Register 3 */
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#define TLMMR4 0x0300 /* CM: Memory Mapping Register 4 */
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#define TLMMR5 0x0340 /* CM: Memory Mapping Register 5 */
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#define TLMMR6 0x0380 /* CM: Memory Mapping Register 6 */
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#define TLMMR7 0x03c0 /* CM: Memory Mapping Register 7 */
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#define TLFADR0 0x0600 /* MI: Failing Address Register 0 */
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#define TLFADR1 0x0640 /* MI: Failing Address Register 1 */
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#define TLESR0 0x0680 /* CMI: Error Syndrome Register 0 */
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#define TLESR1 0x06c0 /* CMI: Error Syndrome Register 1 */
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#define TLESR2 0x0700 /* CMI: Error Syndrome Register 2 */
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#define TLESR3 0x0740 /* CMI: Error Syndrome Register 3 */
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#define TLILID0 0x0a00 /* I: Int. Level 0 IDENT Register */
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#define TLILID1 0x0a40 /* I: Int. Level 1 IDENT Register */
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#define TLILID2 0x0a80 /* I: Int. Level 2 IDENT Register */
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#define TLILID3 0x0ac0 /* I: Int. Level 3 IDENT Register */
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#define TLCPUMASK 0x0b00 /* I: CPU Interrupt Mask Register */
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#define TLMBPTR 0x0c00 /* I: Mailbox Pointer Register */
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#define TLEPAERR 0x1500 /* C: ADG error register */
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/*
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* Registers shared between TurboLaser nodes, offsets from the
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* TurboLaser Broadcast Base.
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*/
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#define TLPRIVATE 0x0000 /* CMI: private "global" space */
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#define TLIPINTR 0x0040 /* C: Interprocessor Int. Register */
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#define TLIOINTR4 0x0100 /* C: I/O Interrupt Register 4 */
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#define TLIOINTR5 0x0140 /* C: I/O Interrupt Register 5 */
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#define TLIOINTR6 0x0180 /* C: I/O Interrupt Register 6 */
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#define TLIOINTR7 0x01c0 /* C: I/O Interrupt Register 7 */
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#define TLIOINTR8 0x0200 /* C: I/O Interrupt Register 8 */
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#define TLWSDQR4 0x0400 /* C: Win Spc Dcr Que Ctr Reg 4 */
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#define TLWSDQR5 0x0440 /* C: Win Spc Dcr Que Ctr Reg 5 */
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#define TLWSDQR6 0x0480 /* C: Win Spc Dcr Que Ctr Reg 6 */
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#define TLWSDQR7 0x04c0 /* C: Win Spc Dcr Que Ctr Reg 7 */
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#define TLWSDQR8 0x0500 /* C: Win Spc Dcr Que Ctr Reg 8 */
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#define TLRMDQRX 0x0600 /* C: Mem Chan Dcr Que Ctr Reg X */
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#define TLRMDQR8 0x0640 /* C: Mem Chan Dcr Que Ctr Reg 8 */
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#define TLRDRD 0x0800 /* C: CSR Read Data Rtn Data Reg */
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#define TLRDRE 0x0840 /* C: CSR Read Data Rtn Error Reg */
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#define TLMCR 0x1880 /* M: Memory Control Register */
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/*
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* TLDEV - Device Register
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*
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* Access: R/W
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*
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* Notes:
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* Register is loaded during initialization with information
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* that identifies a node. A zero value indicates a non-initialized
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* (slot empty) node.
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*
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* Bits 0-15 contain the hardware device type, bits 16-23
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* the board's software revision, and bits 24-31 the board's
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* hardware revision.
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*
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* The device type portion is laid out as follows:
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*
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* Bit 15: identifies a CPU
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* Bit 14: identifies a memory board
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* Bit 13: identifies an I/O board
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* Bits 0-7: specify the ID of a node type
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*/
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#define TLDEV_DTYPE_MASK 0x0000ffff
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#define TLDEV_DTYPE_KFTHA 0x2000 /* KFTHA board, I/O */
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#define TLDEV_DTYPE_KFTIA 0x2020 /* KFTIA board, I/O */
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#define TLDEV_DTYPE_MS7CC 0x5000 /* Memory board */
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#define TLDEV_DTYPE_SCPU4 0x8011 /* 1 CPU, 4mb cache */
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#define TLDEV_DTYPE_SCPU16 0x8012 /* 1 CPU, 16mb cache */
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#define TLDEV_DTYPE_DCPU4 0x8014 /* 2 CPU, 4mb cache */
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#define TLDEV_DTYPE_DCPU16 0x8015 /* 2 CPU, 16mb cache */
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#define TLDEV_DTYPE(_val) ((_val) & TLDEV_DTYPE_MASK)
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# define TLDEV_ISCPU(_val) (TLDEV_DTYPE(_val) & 0x8000)
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# define TLDEV_ISMEM(_val) (TLDEV_DTYPE(_val) & 0x4000)
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# define TLDEV_ISIOPORT(_val) (TLDEV_DTYPE(_val) & 0x2000)
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#define TLDEV_SWREV(_val) (((_val) >> 16) & 0xff)
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#define TLDEV_HWREV(_val) (((_val) >> 24) & 0xff)
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/*
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* TLBER - Bus Error Register
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*
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* Access: R/W
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*
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* Notes:
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* This register contains information about TLSB errors detected by
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* nodes on the TLSB. The register will become locked when:
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*
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* * Any error occurs and the "lock on first error"
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* bit of the Configuration Register is set.
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*
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* * Any bit other than 20-23 (DS0-DS3) becomes set.
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*
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* and will remain locked until either:
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*
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* * All bits in the TLBER are cleared.
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*
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* * The "lock on first error" bit is cleared.
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*
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* TLBER locking is intended for diagnosic purposes only, and
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* not for general use.
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*/
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#define TLBER_ATCE 0x00000001 /* Addr Transmit Ck Error */
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#define TLBER_APE 0x00000002 /* Addr Parity Error */
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#define TLBER_BAE 0x00000004 /* Bank Avail Violation Error */
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#define TLBER_LKTO 0x00000008 /* Bank Lock Timeout */
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#define TLBER_NAE 0x00000010 /* No Ack Error */
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#define TLBER_RTCE 0x00000020 /* Read Transmit Ck Error */
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#define TLBER_ACKTCE 0x00000040 /* Ack Transmit Ck Error */
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#define TLBER_MMRE 0x00000080 /* Mem Mapping Register Error */
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#define TLBER_FNAE 0x00000100 /* Fatal No Ack Error */
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#define TLBER_REQDE 0x00000200 /* Request Deassertion Error */
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#define TLBER_ATDE 0x00000400 /* Addredd Transmitter During Error */
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#define TLBER_UDE 0x00010000 /* Uncorrectable Data Error */
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#define TLBER_CWDE 0x00020000 /* Correctable Write Data Error */
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#define TLBER_CRDE 0x00040000 /* Correctable Read Data Error */
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#define TLBER_CRDE2 0x00080000 /* ...ditto... */
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#define TLBER_DS0 0x00100000 /* Data Synd 0 */
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#define TLBER_DS1 0x00200000 /* Data Synd 1 */
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#define TLBER_DS2 0x00400000 /* Data Synd 2 */
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#define TLBER_DS3 0x00800000 /* Data Synd 3 */
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#define TLBER_DTDE 0x01000000 /* Data Transmitter During Error */
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#define TLBER_FDTCE 0x02000000 /* Fatal Data Transmit Ck Error */
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#define TLBER_UACKE 0x04000000 /* Unexpected Ack Error */
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#define TLBER_ABTCE 0x08000000 /* Addr Bus Transmit Error */
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#define TLBER_DCTCE 0x10000000 /* Data Control Transmit Ck Error */
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#define TLBER_SEQE 0x20000000 /* Sequence Error */
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#define TLBER_DSE 0x40000000 /* Data Status Error */
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#define TLBER_DTO 0x80000000 /* Data Timeout Error */
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/*
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* TLCNR - Configuration Register
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*
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* Access: R/W
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*/
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#define TLCNR_CWDD 0x00000001 /* Corr Write Data Err INTR Dis */
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#define TLCNR_CRDD 0x00000002 /* Corr Read Data Err INTR Dis */
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#define TLCNR_LKTOD 0x00000004 /* Bank Lock Timeout Disable */
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#define TLCNR_DTOD 0x00000008 /* Data Timeout Disable */
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#define TLCNR_STF_A 0x00001000 /* Self-Test Fail A */
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#define TLCNR_STF_B 0x00002000 /* Self-Test Fail B */
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#define TLCNR_HALT_A 0x00100000 /* Halt A */
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#define TLCNR_HALT_B 0x00200000 /* Halt B */
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#define TLCNR_RSTSTAT 0x10000000 /* Reset Status */
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#define TLCNR_NRST 0x40000000 /* Node Reset */
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#define TLCNR_LOFE 0x80000000 /* Lock On First Error */
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#define TLCNR_NODE_MASK 0x000000f0 /* Node ID mask */
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#define TLCNR_NODE_SHIFT 4
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#define TLCNR_VCNT_MASK 0x00000f00 /* VCNT mask */
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#define TLCNR_VCNT_SHIFT 8
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/*
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* TLVID - Virtual ID Register
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*
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* Access: R/W
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*
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* Notes:
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* Virtual units can be CPUs or Memory boards. The units are
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* are addressed using virtual IDs. These virtual IDs are assigned
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* by writing to the TLVID register. The upper 24 bits of this
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* register are reserved and must be written as `0'.
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*/
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#define TLVID_VIDA_MASK 0x0000000f /* Virtual ID for unit 0 */
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#define TLVID_VIDA_SHIFT 0
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#define TLVID_VIDB_MASK 0x000000f0 /* Virtual ID for unit 1 */
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#define TLVID_VIDB_SHIFT 4
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/*
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* TLMMRn - Memory Mapping Registers
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*
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* Access: W
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*
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* Notes:
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* Contains mapping information for doing a bank-decode.
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*/
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#define TLMMR_INTMASK 0x00000003 /* Valid bits in Interleave */
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#define TLMMR_ADRMASK 0x000000f0 /* Valid bits in Address */
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#define TLMMR_SBANK 0x00000800 /* Single-bank indicator */
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#define TLMMR_VALID 0x80000000 /* Indicated mapping is valid */
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#define TLMMR_INTLV_MASK 0x00000700 /* Mask for interleave value */
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#define TLMMR_INTLV_SHIFT 8
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#define TLMMR_ADDRESS_MASK 0x03fff000 /* Mask for address value */
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#define TLMMR_ADDRESS_SHIFT 12
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/*
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* TLFADRn - Failing Address Registers
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*
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* Access: R/W
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*
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* Notes:
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* These registers contain status information for a failed address.
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* Not all nodes preserve this information. The validation bits
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* indicate the validity of a given field.
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*/
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