1d4fd9f5a8
The platform that supports SMP currently is a SWARM with a dual-core Sibyte processor. The kernel config file to use is SWARM_SMP. Reviewed by: imp, rrs
87 lines
2.9 KiB
C
87 lines
2.9 KiB
C
/*-
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* Copyright (c) 2004 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_INTR_MACHDEP_H_
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#define _MACHINE_INTR_MACHDEP_H_
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#ifdef TARGET_XLR_XLS
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/*
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* XLR/XLS uses its own intr_machdep.c and has
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* a different number of interupts. This probably
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* should be placed somewhere else.
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*/
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struct mips_intrhand {
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struct intr_event *mih_event;
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driver_intr_t *mih_disable;
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volatile long *cntp; /* interrupt counter */
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};
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extern struct mips_intrhand mips_intr_handlers[];
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#define XLR_MAX_INTR 64
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#else
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#define NHARD_IRQS 6
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#define NSOFT_IRQS 2
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#endif
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struct trapframe;
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void cpu_init_interrupts(void);
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void cpu_establish_hardintr(const char *, driver_filter_t *, driver_intr_t *,
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void *, int, int, void **);
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void cpu_establish_softintr(const char *, driver_filter_t *, void (*)(void*),
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void *, int, int, void **);
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void cpu_intr(struct trapframe *);
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/*
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* Allow a platform to override the default hard interrupt mask and unmask
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* functions. The 'arg' can be cast safely to an 'int' and holds the mips
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* hard interrupt number to mask or unmask.
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*/
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typedef void (*cpu_intr_mask_t)(void *arg);
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typedef void (*cpu_intr_unmask_t)(void *arg);
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void cpu_set_hardintr_mask_func(cpu_intr_mask_t func);
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void cpu_set_hardintr_unmask_func(cpu_intr_unmask_t func);
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/*
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* Opaque datatype that represents intr counter
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*/
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typedef unsigned long* mips_intrcnt_t;
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mips_intrcnt_t mips_intrcnt_create(const char *);
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void mips_intrcnt_setname(mips_intrcnt_t, const char *);
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static __inline void
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mips_intrcnt_inc(mips_intrcnt_t counter)
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{
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if (counter)
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atomic_add_long(counter, 1);
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}
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#endif /* !_MACHINE_INTR_MACHDEP_H_ */
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