d1d7df1905
On alpha, PAL is involved in context management and after wiring the CPU (in alpha_init()) a context switch was performed to tell PAL about the context. This was bogusly brought over to ia64 where it introduced bugs, because we restored the context from a mostly uninitialized PCB. The cleanup constitutes: o Remove the unused arguments from ia64_init(). o Don't return from ia64_init(), but instead call mi_startup() directly. This reduces the amount of muckery in assembly and also allows for the next bullet: o Save our currect context prior to calling mi_startup(). The reason for this is that many threads are created from thread0 by cloning the PCB. By saving our context in the PCB, we have something sane to clone. It also ensures that a cloned thread that does not alter the context in any way will return to the saved context, where we're ready for the eventuality with a nice, user unfriendly panic(). The cleanup fixes at least the following bugs: o Entering mi_startup() with the RSE in enforced lazy mode. o Re-execution of ia64_init() in certain "lab" conditions. While here, add proper unwind directives to __start() so that the unwind knows it has reached the bottom of the (call) stack. Approved by: re@ (blanket)
440 lines
8.7 KiB
ArmAsm
440 lines
8.7 KiB
ArmAsm
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <machine/asm.h>
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#include <machine/ia64_cpu.h>
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#include <machine/fpu.h>
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#include <machine/pte.h>
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#include <sys/syscall.h>
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#include <assym.s>
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#ifndef EVCNT_COUNTERS
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#define _LOCORE
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#include <machine/intrcnt.h>
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#endif
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.section .data.proc0,"aw"
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.global kstack
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.align PAGE_SIZE
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kstack: .space KSTACK_PAGES * PAGE_SIZE
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.text
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/*
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* Not really a leaf but we can't return.
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* The EFI loader passes the physical address of the bootinfo block in
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* register r8.
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*/
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ENTRY(__start, 1)
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.prologue
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.save rp,r0
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.body
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{ .mlx
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mov ar.rsc=0
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movl r16=ia64_vector_table // set up IVT early
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;;
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}
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{ .mlx
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mov cr.iva=r16
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movl r16=kstack
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;;
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}
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{ .mmi
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srlz.i
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;;
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ssm IA64_PSR_DFH
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mov r17=KSTACK_PAGES*PAGE_SIZE-SIZEOF_PCB-SIZEOF_TRAPFRAME-16
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;;
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}
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{ .mlx
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add sp=r16,r17 // proc0's stack
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movl gp=__gp // find kernel globals
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;;
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}
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{ .mlx
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mov ar.bspstore=r16 // switch backing store
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movl r16=pa_bootinfo
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;;
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}
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st8 [r16]=r8 // save the PA of the bootinfo block
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loadrs // invalidate regs
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;;
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mov ar.rsc=3 // turn rse back on
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;;
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alloc r16=ar.pfs,0,0,1,0
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;;
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movl out0=0 // we are linked at the right address
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;; // we just need to process fptrs
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br.call.sptk.many rp=_reloc
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;;
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br.call.sptk.many rp=ia64_init
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;;
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/* NOTREACHED */
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1: br.cond.sptk.few 1b
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END(__start)
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/*
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* fork_trampoline()
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*
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* Arrange for a function to be invoked neatly, after a cpu_switch().
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*
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* Invokes fork_exit() passing in three arguments: a callout function, an
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* argument to the callout, and a trapframe pointer. For child processes
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* returning from fork(2), the argument is a pointer to the child process.
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*
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* The callout function and its argument is in the trapframe in scratch
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* registers r2 and r3.
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*/
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ENTRY(fork_trampoline, 0)
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.prologue
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.save rp,r0
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.body
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{ .mmi
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alloc r14=ar.pfs,0,0,3,0
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add r15=32+SIZEOF_SPECIAL+8,sp
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add r16=32+SIZEOF_SPECIAL+16,sp
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;;
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}
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{ .mmi
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ld8 out0=[r15]
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ld8 out1=[r16]
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nop 0
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}
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{ .mfb
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add out2=16,sp
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nop 0
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br.call.sptk rp=fork_exit
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;;
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}
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// If we get back here, it means we're a user space process that's
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// the immediate result of fork(2).
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.global enter_userland
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.type enter_userland, @function
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enter_userland:
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{ .mmi
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add r14=24,sp
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;;
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ld8 r14=[r14]
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nop 0
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;;
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}
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{ .mbb
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cmp.eq p6,p7=r0,r14
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(p6) br.sptk exception_restore
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(p7) br.sptk epc_syscall_return
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;;
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}
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END(fork_trampoline)
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#ifdef SMP
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/*
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* AP wake-up entry point. The handoff state is similar as for the BSP,
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* as described on page 3-9 of the IPF SAL Specification. The difference
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* lies in the contents of register b0. For APs this register holds the
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* return address into the SAL rendezvous routine.
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*
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* Note that we're responsible for clearing the IRR bit by reading cr.ivr
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* and issuing the EOI to the local SAPIC.
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*/
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.align 32
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ENTRY(os_boot_rendez,0)
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mov r16=cr.ivr // clear IRR bit
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;;
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srlz.d
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mov cr.eoi=r0 // ACK the wake-up
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;;
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srlz.d
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rsm IA64_PSR_IC|IA64_PSR_I
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;;
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mov r16 = (5<<8)|(PAGE_SHIFT<<2)|1
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movl r17 = 5<<61
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;;
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mov rr[r17] = r16
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;;
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srlz.d
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mov r16 = (6<<8)|(28<<2)
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movl r17 = 6<<61
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;;
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mov rr[r17] = r16
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;;
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srlz.d
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mov r16 = (7<<8)|(28<<2)
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movl r17 = 7<<61
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;;
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mov rr[r17] = r16
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;;
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srlz.d
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mov r16 = (PTE_P|PTE_MA_WB|PTE_A|PTE_D|PTE_PL_KERN|PTE_AR_RWX)
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mov r18 = 28<<2
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;;
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mov cr.ifa = r17
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mov cr.itir = r18
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ptr.d r17, r18
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ptr.i r17, r18
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;;
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srlz.i
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;;
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itr.d dtr[r0] = r16
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;;
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itr.i itr[r0] = r16
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;;
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srlz.i
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;;
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1: mov r16 = ip
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add r17 = 2f-1b, r17
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movl r18 = (IA64_PSR_AC|IA64_PSR_BN|IA64_PSR_DFH|IA64_PSR_DT|IA64_PSR_IC|IA64_PSR_IT|IA64_PSR_RT)
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;;
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add r17 = r17, r16
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mov cr.ipsr = r18
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mov cr.ifs = r0
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;;
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mov cr.iip = r17
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;;
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rfi
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.align 32
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2:
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{ .mlx
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mov ar.rsc = 0
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movl r16 = ia64_vector_table // set up IVT early
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;;
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}
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{ .mlx
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mov cr.iva = r16
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movl r16 = ap_stack
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;;
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}
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{ .mmi
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srlz.i
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;;
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ld8 r16 = [r16]
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mov r18 = KSTACK_PAGES*PAGE_SIZE-SIZEOF_PCB-SIZEOF_TRAPFRAME-16
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;;
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}
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{ .mlx
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mov ar.bspstore = r16
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movl gp = __gp
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;;
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}
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{ .mmi
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loadrs
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;;
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alloc r17 = ar.pfs, 0, 0, 0, 0
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add sp = r18, r16
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;;
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}
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{ .mfb
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mov ar.rsc = 3
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nop 0
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br.call.sptk.few rp = ia64_ap_startup
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;;
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}
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/* NOT REACHED */
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9:
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{ .mfb
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nop 0
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nop 0
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br.sptk 9b
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;;
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}
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END(os_boot_rendez)
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#endif /* !SMP */
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/*
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* Create a default interrupt name table. The first entry (vector 0) is
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* hardwaired to the clock interrupt.
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*/
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.data
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.align 8
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EXPORT(intrnames)
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.ascii "clock"
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.fill INTRNAME_LEN - 5 - 1, 1, ' '
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.byte 0
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intr_n = 0
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.rept INTRCNT_COUNT - 1
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.ascii "#"
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.byte intr_n / 100 + '0'
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.byte (intr_n % 100) / 10 + '0'
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.byte intr_n % 10 + '0'
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.fill INTRNAME_LEN - 1 - 3 - 1, 1, ' '
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.byte 0
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intr_n = intr_n + 1
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.endr
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EXPORT(eintrnames)
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.align 8
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EXPORT(intrcnt)
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.fill INTRCNT_COUNT, 8, 0
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EXPORT(eintrcnt)
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.text
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// in0: image base
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STATIC_ENTRY(_reloc, 1)
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alloc loc0=ar.pfs,1,2,0,0
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mov loc1=rp
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;;
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movl r15=@gprel(_DYNAMIC) // find _DYNAMIC etc.
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movl r2=@gprel(fptr_storage)
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movl r3=@gprel(fptr_storage_end)
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;;
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add r15=r15,gp // relocate _DYNAMIC etc.
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add r2=r2,gp
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add r3=r3,gp
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;;
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1: ld8 r16=[r15],8 // read r15->d_tag
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;;
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ld8 r17=[r15],8 // and r15->d_val
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;;
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cmp.eq p6,p0=DT_NULL,r16 // done?
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(p6) br.cond.dpnt.few 2f
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;;
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cmp.eq p6,p0=DT_RELA,r16
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;;
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(p6) add r18=r17,in0 // found rela section
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;;
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cmp.eq p6,p0=DT_RELASZ,r16
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;;
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(p6) mov r19=r17 // found rela size
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;;
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cmp.eq p6,p0=DT_SYMTAB,r16
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;;
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(p6) add r20=r17,in0 // found symbol table
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;;
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(p6) setf.sig f8=r20
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;;
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cmp.eq p6,p0=DT_SYMENT,r16
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;;
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(p6) setf.sig f9=r17 // found symbol entry size
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;;
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cmp.eq p6,p0=DT_RELAENT,r16
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;;
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(p6) mov r22=r17 // found rela entry size
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;;
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br.sptk.few 1b
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2:
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ld8 r15=[r18],8 // read r_offset
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;;
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ld8 r16=[r18],8 // read r_info
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add r15=r15,in0 // relocate r_offset
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;;
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ld8 r17=[r18],8 // read r_addend
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sub r19=r19,r22 // update relasz
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extr.u r23=r16,0,32 // ELF64_R_TYPE(r16)
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;;
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cmp.eq p6,p0=R_IA64_NONE,r23
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(p6) br.cond.dpnt.few 3f
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;;
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cmp.eq p6,p0=R_IA64_REL64LSB,r23
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(p6) br.cond.dptk.few 4f
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;;
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extr.u r16=r16,32,32 // ELF64_R_SYM(r16)
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;;
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setf.sig f10=r16 // so we can multiply
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;;
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xma.lu f10=f10,f9,f8 // f10=symtab + r_sym*syment
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;;
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getf.sig r16=f10
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;;
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add r16=8,r16 // address of st_value
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;;
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ld8 r16=[r16] // read symbol value
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;;
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add r16=r16,in0 // relocate symbol value
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;;
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cmp.eq p6,p0=R_IA64_DIR64LSB,r23
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(p6) br.cond.dptk.few 5f
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;;
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cmp.eq p6,p0=R_IA64_FPTR64LSB,r23
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(p6) br.cond.dptk.few 6f
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;;
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3:
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cmp.ltu p6,p0=0,r19 // more?
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(p6) br.cond.dptk.few 2b // loop
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mov r8=0 // success return value
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br.cond.sptk.few 9f // done
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4:
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add r16=in0,r17 // BD + A
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;;
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st8 [r15]=r16 // word64 (LSB)
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br.cond.sptk.few 3b
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5:
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add r16=r16,r17 // S + A
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;;
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st8 [r15]=r16 // word64 (LSB)
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br.cond.sptk.few 3b
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6:
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movl r17=@gprel(fptr_storage)
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;;
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add r17=r17,gp // start of fptrs
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;;
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7: cmp.geu p6,p0=r17,r2 // end of fptrs?
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(p6) br.cond.dpnt.few 8f // can't find existing fptr
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ld8 r20=[r17] // read function from fptr
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;;
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cmp.eq p6,p0=r16,r20 // same function?
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;;
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(p6) st8 [r15]=r17 // reuse fptr
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(p6) br.cond.sptk.few 3b // done
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add r17=16,r17 // next fptr
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br.cond.sptk.few 7b
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8: // allocate new fptr
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mov r8=1 // failure return value
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cmp.geu p6,p0=r2,r3 // space left?
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(p6) br.cond.dpnt.few 9f // bail out
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st8 [r15]=r2 // install fptr
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st8 [r2]=r16,8 // write fptr address
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;;
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st8 [r2]=gp,8 // write fptr gp
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br.cond.sptk.few 3b
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9:
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mov ar.pfs=loc0
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mov rp=loc1
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;;
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br.ret.sptk.few rp
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END(_reloc)
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.data
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.align 16
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.global fptr_storage
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fptr_storage:
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.space 4096*16 // XXX
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fptr_storage_end:
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