819 lines
20 KiB
C
819 lines
20 KiB
C
/* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93
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* JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta
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* $FreeBSD$
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*/
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/*
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* machAsmDefs.h --
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*
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* Macros used when writing assembler programs.
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*
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* Copyright (C) 1989 Digital Equipment Corporation.
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies.
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* Digital Equipment Corporation makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h,
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* v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL)
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*/
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#ifndef _MACHINE_ASM_H_
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#define _MACHINE_ASM_H_
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#ifndef NO_REG_DEFS
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#include <machine/regdef.h>
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#endif
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#include <machine/endian.h>
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#include <machine/cdefs.h>
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#undef __FBSDID
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#if !defined(lint) && !defined(STRIP_FBSDID)
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#define __FBSDID(s) .ident s
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#else
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#define __FBSDID(s) /* nothing */
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#endif
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/*
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* Define -pg profile entry code.
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* Must always be noreorder, must never use a macro instruction
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* Final addiu to t9 must always equal the size of this _KERN_MCOUNT
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*/
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#define _KERN_MCOUNT \
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.set push; \
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.set noreorder; \
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.set noat; \
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subu sp,sp,16; \
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sw t9,12(sp); \
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move AT,ra; \
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lui t9,%hi(_mcount); \
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addiu t9,t9,%lo(_mcount); \
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jalr t9; \
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nop; \
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lw t9,4(sp); \
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addiu sp,sp,8; \
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addiu t9,t9,40; \
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.set pop;
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#ifdef GPROF
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#define MCOUNT _KERN_MCOUNT
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#else
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#define MCOUNT
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#endif
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#define _C_LABEL(x) x
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/*
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* Endian-independent assembly-code aliases for unaligned memory accesses.
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*/
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#if BYTE_ORDER == LITTLE_ENDIAN
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#define LWLO lwl
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#define LWHI lwr
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#define SWLO swl
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#define SWHI swr
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#endif
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#if BYTE_ORDER == BIG_ENDIAN
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#define LWLO lwr
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#define LWHI lwl
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#define SWLO swr
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#define SWHI swl
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#endif
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#ifdef USE_AENT
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#define AENT(x) \
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.aent x, 0
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#else
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#define AENT(x)
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#endif
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/*
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* WARN_REFERENCES: create a warning if the specified symbol is referenced
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*/
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#define WARN_REFERENCES(_sym,_msg) \
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.section .gnu.warning. ## _sym ; .ascii _msg ; .text
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/*
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* These are temp registers whose names can be used in either the old
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* or new ABI, although they map to different physical registers. In
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* the old ABI, they map to t4-t7, and in the new ABI, they map to a4-a7.
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*
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* Because they overlap with the last 4 arg regs in the new ABI, ta0-ta3
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* should be used only when we need more than t0-t3.
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*/
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#if defined(__mips_n32) || defined(__mips_n64)
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#define ta0 $8
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#define ta1 $9
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#define ta2 $10
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#define ta3 $11
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#else
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#define ta0 $12
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#define ta1 $13
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#define ta2 $14
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#define ta3 $15
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#endif /* __mips_n32 || __mips_n64 */
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#ifdef __ELF__
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# define _C_LABEL(x) x
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#else
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# define _C_LABEL(x) _ ## x
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#endif
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/*
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* WEAK_ALIAS: create a weak alias.
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*/
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#define WEAK_ALIAS(alias,sym) \
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.weak alias; \
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alias = sym
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/*
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* STRONG_ALIAS: create a strong alias.
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*/
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#define STRONG_ALIAS(alias,sym) \
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.globl alias; \
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alias = sym
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#define GLOBAL(sym) \
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.globl sym; sym:
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#define ENTRY(sym) \
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.text; .globl sym; .ent sym; sym:
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#define ASM_ENTRY(sym) \
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.text; .globl sym; .type sym,@function; sym:
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/*
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* LEAF
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* A leaf routine does
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* - call no other function,
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* - never use any register that callee-saved (S0-S8), and
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* - not use any local stack storage.
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*/
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#define LEAF(x) \
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.globl _C_LABEL(x); \
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.ent _C_LABEL(x), 0; \
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_C_LABEL(x): ; \
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.frame sp, 0, ra; \
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MCOUNT
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/*
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* LEAF_NOPROFILE
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* No profilable leaf routine.
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*/
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#define LEAF_NOPROFILE(x) \
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.globl _C_LABEL(x); \
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.ent _C_LABEL(x), 0; \
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_C_LABEL(x): ; \
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.frame sp, 0, ra
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/*
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* XLEAF
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* declare alternate entry to leaf routine
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*/
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#define XLEAF(x) \
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.globl _C_LABEL(x); \
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AENT (_C_LABEL(x)); \
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_C_LABEL(x):
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/*
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* NESTED
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* A function calls other functions and needs
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* therefore stack space to save/restore registers.
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*/
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#define NESTED(x, fsize, retpc) \
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.globl _C_LABEL(x); \
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.ent _C_LABEL(x), 0; \
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_C_LABEL(x): ; \
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.frame sp, fsize, retpc; \
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MCOUNT
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/*
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* NESTED_NOPROFILE(x)
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* No profilable nested routine.
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*/
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#define NESTED_NOPROFILE(x, fsize, retpc) \
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.globl _C_LABEL(x); \
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.ent _C_LABEL(x), 0; \
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_C_LABEL(x): ; \
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.frame sp, fsize, retpc
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/*
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* XNESTED
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* declare alternate entry point to nested routine.
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*/
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#define XNESTED(x) \
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.globl _C_LABEL(x); \
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AENT (_C_LABEL(x)); \
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_C_LABEL(x):
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/*
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* END
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* Mark end of a procedure.
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*/
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#define END(x) \
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.end _C_LABEL(x)
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/*
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* IMPORT -- import external symbol
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*/
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#define IMPORT(sym, size) \
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.extern _C_LABEL(sym),size
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/*
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* EXPORT -- export definition of symbol
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*/
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#define EXPORT(x) \
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.globl _C_LABEL(x); \
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_C_LABEL(x):
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/*
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* VECTOR
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* exception vector entrypoint
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* XXX: regmask should be used to generate .mask
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*/
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#define VECTOR(x, regmask) \
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.ent _C_LABEL(x),0; \
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EXPORT(x); \
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#define VECTOR_END(x) \
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EXPORT(x ## End); \
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END(x)
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#define KSEG0TEXT_START
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#define KSEG0TEXT_END
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#define KSEG0TEXT .text
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/*
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* Macros to panic and printf from assembly language.
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*/
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#define PANIC(msg) \
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PTR_LA a0, 9f; \
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jal _C_LABEL(panic); \
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nop; \
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MSG(msg)
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#define PANIC_KSEG0(msg, reg) PANIC(msg)
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#define PRINTF(msg) \
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PTR_LA a0, 9f; \
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jal _C_LABEL(printf); \
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nop; \
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MSG(msg)
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#define MSG(msg) \
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.rdata; \
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9: .asciiz msg; \
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.text
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#define ASMSTR(str) \
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.asciiz str; \
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.align 3
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/*
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* Call ast if required
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*/
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#define DO_AST \
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44: \
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PTR_LA s0, _C_LABEL(disableintr) ;\
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jalr s0 ;\
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nop ;\
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move a0, v0 ;\
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GET_CPU_PCPU(s1) ;\
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lw s3, PC_CURPCB(s1) ;\
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lw s1, PC_CURTHREAD(s1) ;\
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lw s2, TD_FLAGS(s1) ;\
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li s0, TDF_ASTPENDING | TDF_NEEDRESCHED;\
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and s2, s0 ;\
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PTR_LA s0, _C_LABEL(restoreintr) ;\
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jalr s0 ;\
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nop ;\
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beq s2, zero, 4f ;\
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nop ;\
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PTR_LA s0, _C_LABEL(ast) ;\
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jalr s0 ;\
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PTR_ADDU a0, s3, U_PCB_REGS ;\
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j 44b ;\
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nop ;\
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4:
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/*
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* XXX retain dialects XXX
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*/
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#define ALEAF(x) XLEAF(x)
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#define NLEAF(x) LEAF_NOPROFILE(x)
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#define NON_LEAF(x, fsize, retpc) NESTED(x, fsize, retpc)
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#define NNON_LEAF(x, fsize, retpc) NESTED_NOPROFILE(x, fsize, retpc)
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#if defined(__mips_o32)
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#define SZREG 4
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#else
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#define SZREG 8
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#endif
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#if defined(__mips_o32) || defined(__mips_o64)
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#define ALSK 7 /* stack alignment */
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#define ALMASK -7 /* stack alignment */
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#define SZFPREG 4
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#define FP_L lwc1
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#define FP_S swc1
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#else
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#define ALSK 15 /* stack alignment */
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#define ALMASK -15 /* stack alignment */
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#define SZFPREG 8
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#define FP_L ldc1
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#define FP_S sdc1
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#endif
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/*
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* standard callframe {
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* register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1)
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* register_t cf_args[4]; arg0 - arg3 (only on o32 and o64)
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* register_t cf_gp; global pointer (only on n32 and n64)
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* register_t cf_sp; frame pointer
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* register_t cf_ra; return address
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* };
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*/
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#if defined(__mips_o32) || defined(__mips_o64)
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#define CALLFRAME_SIZ (SZREG * (4 + 2))
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#define CALLFRAME_S0 0
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#elif defined(__mips_n32) || defined(__mips_n64)
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#define CALLFRAME_SIZ (SZREG * 4)
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#define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG)
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#endif
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#ifndef _KERNEL
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#define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG)
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#endif
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#define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG)
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#define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG)
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/*
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* While it would be nice to be compatible with the SGI
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* REG_L and REG_S macros, because they do not take parameters, it
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* is impossible to use them with the _MIPS_SIM_ABIX32 model.
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*
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* These macros hide the use of mips3 instructions from the
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* assembler to prevent the assembler from generating 64-bit style
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* ABI calls.
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*/
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#if _MIPS_SZPTR == 32
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#define PTR_ADD add
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#define PTR_ADDI addi
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#define PTR_ADDU addu
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#define PTR_ADDIU addiu
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#define PTR_SUB add
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#define PTR_SUBI subi
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#define PTR_SUBU subu
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#define PTR_SUBIU subu
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#define PTR_L lw
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#define PTR_LA la
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#define PTR_S sw
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#define PTR_SLL sll
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#define PTR_SLLV sllv
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#define PTR_SRL srl
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#define PTR_SRLV srlv
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#define PTR_SRA sra
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#define PTR_SRAV srav
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#define PTR_LL ll
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#define PTR_SC sc
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#define PTR_WORD .word
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#define PTR_SCALESHIFT 2
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#else /* _MIPS_SZPTR == 64 */
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#define PTR_ADD dadd
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#define PTR_ADDI daddi
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#define PTR_ADDU daddu
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#define PTR_ADDIU daddiu
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#define PTR_SUB dadd
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#define PTR_SUBI dsubi
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#define PTR_SUBU dsubu
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#define PTR_SUBIU dsubu
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#define PTR_L ld
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#define PTR_LA dla
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#define PTR_S sd
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#define PTR_SLL dsll
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#define PTR_SLLV dsllv
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#define PTR_SRL dsrl
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#define PTR_SRLV dsrlv
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#define PTR_SRA dsra
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#define PTR_SRAV dsrav
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#define PTR_LL lld
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#define PTR_SC scd
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#define PTR_WORD .dword
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#define PTR_SCALESHIFT 3
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#endif /* _MIPS_SZPTR == 64 */
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#if _MIPS_SZINT == 32
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#define INT_ADD add
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#define INT_ADDI addi
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#define INT_ADDU addu
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#define INT_ADDIU addiu
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#define INT_SUB add
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#define INT_SUBI subi
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#define INT_SUBU subu
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#define INT_SUBIU subu
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#define INT_L lw
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#define INT_LA la
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#define INT_S sw
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#define INT_SLL sll
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#define INT_SLLV sllv
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#define INT_SRL srl
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#define INT_SRLV srlv
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#define INT_SRA sra
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#define INT_SRAV srav
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#define INT_LL ll
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#define INT_SC sc
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#define INT_WORD .word
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#define INT_SCALESHIFT 2
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#else
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#define INT_ADD dadd
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#define INT_ADDI daddi
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#define INT_ADDU daddu
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#define INT_ADDIU daddiu
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#define INT_SUB dadd
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#define INT_SUBI dsubi
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#define INT_SUBU dsubu
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#define INT_SUBIU dsubu
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#define INT_L ld
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#define INT_LA dla
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#define INT_S sd
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#define INT_SLL dsll
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#define INT_SLLV dsllv
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#define INT_SRL dsrl
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#define INT_SRLV dsrlv
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#define INT_SRA dsra
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#define INT_SRAV dsrav
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#define INT_LL lld
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#define INT_SC scd
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#define INT_WORD .dword
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#define INT_SCALESHIFT 3
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#endif
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#if _MIPS_SZLONG == 32
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#define LONG_ADD add
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#define LONG_ADDI addi
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#define LONG_ADDU addu
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#define LONG_ADDIU addiu
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#define LONG_SUB add
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#define LONG_SUBI subi
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#define LONG_SUBU subu
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#define LONG_SUBIU subu
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#define LONG_L lw
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#define LONG_LA la
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#define LONG_S sw
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#define LONG_SLL sll
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#define LONG_SLLV sllv
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#define LONG_SRL srl
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#define LONG_SRLV srlv
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#define LONG_SRA sra
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#define LONG_SRAV srav
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#define LONG_LL ll
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#define LONG_SC sc
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#define LONG_WORD .word
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#define LONG_SCALESHIFT 2
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#else
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#define LONG_ADD dadd
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#define LONG_ADDI daddi
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#define LONG_ADDU daddu
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#define LONG_ADDIU daddiu
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#define LONG_SUB dadd
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#define LONG_SUBI dsubi
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#define LONG_SUBU dsubu
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#define LONG_SUBIU dsubu
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#define LONG_L ld
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#define LONG_LA dla
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#define LONG_S sd
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#define LONG_SLL dsll
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#define LONG_SLLV dsllv
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#define LONG_SRL dsrl
|
|
#define LONG_SRLV dsrlv
|
|
#define LONG_SRA dsra
|
|
#define LONG_SRAV dsrav
|
|
#define LONG_LL lld
|
|
#define LONG_SC scd
|
|
#define LONG_WORD .dword
|
|
#define LONG_SCALESHIFT 3
|
|
#endif
|
|
|
|
#if SZREG == 4
|
|
#define REG_L lw
|
|
#define REG_S sw
|
|
#define REG_LI li
|
|
#define REG_ADDU addu
|
|
#define REG_SLL sll
|
|
#define REG_SLLV sllv
|
|
#define REG_SRL srl
|
|
#define REG_SRLV srlv
|
|
#define REG_SRA sra
|
|
#define REG_SRAV srav
|
|
#define REG_LL ll
|
|
#define REG_SC sc
|
|
#define REG_SCALESHIFT 2
|
|
#else
|
|
#define REG_L ld
|
|
#define REG_S sd
|
|
#define REG_LI dli
|
|
#define REG_ADDU daddu
|
|
#define REG_SLL dsll
|
|
#define REG_SLLV dsllv
|
|
#define REG_SRL dsrl
|
|
#define REG_SRLV dsrlv
|
|
#define REG_SRA dsra
|
|
#define REG_SRAV dsrav
|
|
#define REG_LL lld
|
|
#define REG_SC scd
|
|
#define REG_SCALESHIFT 3
|
|
#endif
|
|
|
|
#if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \
|
|
_MIPS_ISA == _MIPS_ISA_MIPS32
|
|
#define MFC0 mfc0
|
|
#define MTC0 mtc0
|
|
#endif
|
|
#if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \
|
|
_MIPS_ISA == _MIPS_ISA_MIPS64
|
|
#define MFC0 dmfc0
|
|
#define MTC0 dmtc0
|
|
#endif
|
|
|
|
#if defined(__mips_o32) || defined(__mips_o64)
|
|
|
|
#ifdef __ABICALLS__
|
|
#define CPRESTORE(r) .cprestore r
|
|
#define CPLOAD(r) .cpload r
|
|
#else
|
|
#define CPRESTORE(r) /* not needed */
|
|
#define CPLOAD(r) /* not needed */
|
|
#endif
|
|
|
|
#define SETUP_GP \
|
|
.set push; \
|
|
.set noreorder; \
|
|
.cpload t9; \
|
|
.set pop
|
|
#define SETUP_GPX(r) \
|
|
.set push; \
|
|
.set noreorder; \
|
|
move r,ra; /* save old ra */ \
|
|
bal 7f; \
|
|
nop; \
|
|
7: .cpload ra; \
|
|
move ra,r; \
|
|
.set pop
|
|
#define SETUP_GPX_L(r,lbl) \
|
|
.set push; \
|
|
.set noreorder; \
|
|
move r,ra; /* save old ra */ \
|
|
bal lbl; \
|
|
nop; \
|
|
lbl: .cpload ra; \
|
|
move ra,r; \
|
|
.set pop
|
|
#define SAVE_GP(x) .cprestore x
|
|
|
|
#define SETUP_GP64(a,b) /* n32/n64 specific */
|
|
#define SETUP_GP64_R(a,b) /* n32/n64 specific */
|
|
#define SETUP_GPX64(a,b) /* n32/n64 specific */
|
|
#define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */
|
|
#define RESTORE_GP64 /* n32/n64 specific */
|
|
#define USE_ALT_CP(a) /* n32/n64 specific */
|
|
#endif /* __mips_o32 || __mips_o64 */
|
|
|
|
#if defined(__mips_o32) || defined(__mips_o64)
|
|
#define REG_PROLOGUE .set push
|
|
#define REG_EPILOGUE .set pop
|
|
#endif
|
|
#if defined(__mips_n32) || defined(__mips_n64)
|
|
#define REG_PROLOGUE .set push ; .set mips3
|
|
#define REG_EPILOGUE .set pop
|
|
#endif
|
|
|
|
#if defined(__mips_n32) || defined(__mips_n64)
|
|
#define SETUP_GP /* o32 specific */
|
|
#define SETUP_GPX(r) /* o32 specific */
|
|
#define SETUP_GPX_L(r,lbl) /* o32 specific */
|
|
#define SAVE_GP(x) /* o32 specific */
|
|
#define SETUP_GP64(a,b) .cpsetup $25, a, b
|
|
#define SETUP_GPX64(a,b) \
|
|
.set push; \
|
|
move b,ra; \
|
|
.set noreorder; \
|
|
bal 7f; \
|
|
nop; \
|
|
7: .set pop; \
|
|
.cpsetup ra, a, 7b; \
|
|
move ra,b
|
|
#define SETUP_GPX64_L(a,b,c) \
|
|
.set push; \
|
|
move b,ra; \
|
|
.set noreorder; \
|
|
bal c; \
|
|
nop; \
|
|
c: .set pop; \
|
|
.cpsetup ra, a, c; \
|
|
move ra,b
|
|
#define RESTORE_GP64 .cpreturn
|
|
#define USE_ALT_CP(a) .cplocal a
|
|
#endif /* __mips_n32 || __mips_n64 */
|
|
|
|
#define mfc0_macro(data, spr) \
|
|
__asm __volatile ("mfc0 %0, $%1" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "i" (spr)); /* inputs */
|
|
|
|
#define mtc0_macro(data, spr) \
|
|
__asm __volatile ("mtc0 %0, $%1" \
|
|
: /* outputs */ \
|
|
: "r" (data), "i" (spr)); /* inputs */
|
|
|
|
#define cfc0_macro(data, spr) \
|
|
__asm __volatile ("cfc0 %0, $%1" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "i" (spr)); /* inputs */
|
|
|
|
#define ctc0_macro(data, spr) \
|
|
__asm __volatile ("ctc0 %0, $%1" \
|
|
: /* outputs */ \
|
|
: "r" (data), "i" (spr)); /* inputs */
|
|
|
|
|
|
#define lbu_macro(data, addr) \
|
|
__asm __volatile ("lbu %0, 0x0(%1)" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "r" (addr)); /* inputs */
|
|
|
|
#define lb_macro(data, addr) \
|
|
__asm __volatile ("lb %0, 0x0(%1)" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "r" (addr)); /* inputs */
|
|
|
|
#define lwl_macro(data, addr) \
|
|
__asm __volatile ("lwl %0, 0x0(%1)" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "r" (addr)); /* inputs */
|
|
|
|
#define lwr_macro(data, addr) \
|
|
__asm __volatile ("lwr %0, 0x0(%1)" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "r" (addr)); /* inputs */
|
|
|
|
#define ldl_macro(data, addr) \
|
|
__asm __volatile ("ldl %0, 0x0(%1)" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "r" (addr)); /* inputs */
|
|
|
|
#define ldr_macro(data, addr) \
|
|
__asm __volatile ("ldr %0, 0x0(%1)" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "r" (addr)); /* inputs */
|
|
|
|
#define sb_macro(data, addr) \
|
|
__asm __volatile ("sb %0, 0x0(%1)" \
|
|
: /* outputs */ \
|
|
: "r" (data), "r" (addr)); /* inputs */
|
|
|
|
#define swl_macro(data, addr) \
|
|
__asm __volatile ("swl %0, 0x0(%1)" \
|
|
: /* outputs */ \
|
|
: "r" (data), "r" (addr)); /* inputs */
|
|
|
|
#define swr_macro(data, addr) \
|
|
__asm __volatile ("swr %0, 0x0(%1)" \
|
|
: /* outputs */ \
|
|
: "r" (data), "r" (addr)); /* inputs */
|
|
|
|
#define sdl_macro(data, addr) \
|
|
__asm __volatile ("sdl %0, 0x0(%1)" \
|
|
: /* outputs */ \
|
|
: "r" (data), "r" (addr)); /* inputs */
|
|
|
|
#define sdr_macro(data, addr) \
|
|
__asm __volatile ("sdr %0, 0x0(%1)" \
|
|
: /* outputs */ \
|
|
: "r" (data), "r" (addr)); /* inputs */
|
|
|
|
#define mfgr_macro(data, gr) \
|
|
__asm __volatile ("move %0, $%1" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "i" (gr)); /* inputs */
|
|
|
|
#define dmfc0_macro(data, spr) \
|
|
__asm __volatile ("dmfc0 %0, $%1" \
|
|
: "=r" (data) /* outputs */ \
|
|
: "i" (spr)); /* inputs */
|
|
|
|
#define dmtc0_macro(data, spr, sel) \
|
|
__asm __volatile ("dmtc0 %0, $%1, %2" \
|
|
: /* no outputs */ \
|
|
: "r" (data), "i" (spr), "i" (sel)); /* inputs */
|
|
|
|
/*
|
|
* The DYNAMIC_STATUS_MASK option adds an additional masking operation
|
|
* when updating the hardware interrupt mask in the status register.
|
|
*
|
|
* This is useful for platforms that need to at run-time mask
|
|
* interrupts based on motherboard configuration or to handle
|
|
* slowly clearing interrupts.
|
|
*
|
|
* XXX this is only currently implemented for mips3.
|
|
*/
|
|
#ifdef MIPS_DYNAMIC_STATUS_MASK
|
|
#define DYNAMIC_STATUS_MASK(sr,scratch) \
|
|
lw scratch, mips_dynamic_status_mask; \
|
|
and sr, sr, scratch
|
|
|
|
#define DYNAMIC_STATUS_MASK_TOUSER(sr,scratch1) \
|
|
ori sr, (MIPS_INT_MASK | MIPS_SR_INT_IE); \
|
|
DYNAMIC_STATUS_MASK(sr,scratch1)
|
|
#else
|
|
#define DYNAMIC_STATUS_MASK(sr,scratch)
|
|
#define DYNAMIC_STATUS_MASK_TOUSER(sr,scratch1)
|
|
#endif
|
|
|
|
#define GET_CPU_PCPU(reg) \
|
|
lw reg, _C_LABEL(pcpup);
|
|
|
|
/*
|
|
* Description of the setjmp buffer
|
|
*
|
|
* word 0 magic number (dependant on creator)
|
|
* 1 RA
|
|
* 2 S0
|
|
* 3 S1
|
|
* 4 S2
|
|
* 5 S3
|
|
* 6 S4
|
|
* 7 S5
|
|
* 8 S6
|
|
* 9 S7
|
|
* 10 SP
|
|
* 11 S8
|
|
* 12 signal mask (dependant on magic)
|
|
* 13 (con't)
|
|
* 14 (con't)
|
|
* 15 (con't)
|
|
*
|
|
* The magic number number identifies the jmp_buf and
|
|
* how the buffer was created as well as providing
|
|
* a sanity check
|
|
*
|
|
*/
|
|
|
|
#define _JB_MAGIC__SETJMP 0xBADFACED
|
|
#define _JB_MAGIC_SETJMP 0xFACEDBAD
|
|
|
|
/* Valid for all jmp_buf's */
|
|
|
|
#define _JB_MAGIC 0
|
|
#define _JB_REG_RA 1
|
|
#define _JB_REG_S0 2
|
|
#define _JB_REG_S1 3
|
|
#define _JB_REG_S2 4
|
|
#define _JB_REG_S3 5
|
|
#define _JB_REG_S4 6
|
|
#define _JB_REG_S5 7
|
|
#define _JB_REG_S6 8
|
|
#define _JB_REG_S7 9
|
|
#define _JB_REG_SP 10
|
|
#define _JB_REG_S8 11
|
|
|
|
/* Only valid with the _JB_MAGIC_SETJMP magic */
|
|
|
|
#define _JB_SIGMASK 12
|
|
|
|
#endif /* !_MACHINE_ASM_H_ */
|