7d018a5c91
Get rid of the macros that spell KSEG0 CACHED and KSEG1 UNCACHED. o) Get rid of some nearby duplicated and unused macros. Reviewed by: imp
571 lines
18 KiB
C
571 lines
18 KiB
C
/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Copyright (C) 1989 Digital Equipment Corporation.
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies.
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* Digital Equipment Corporation makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* from: @(#)cpu.h 8.4 (Berkeley) 1/4/94
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* JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPU_H_
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#define _MACHINE_CPU_H_
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#include <machine/psl.h>
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#include <machine/endian.h>
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#define MIPS_KSEG0_LARGEST_PHYS 0x20000000
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#define MIPS_PHYS_MASK (0x1fffffff)
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#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START)
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#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START)
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#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
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#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
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#define MIPS_IS_KSEG0_ADDR(x) \
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(((vm_offset_t)(x) >= MIPS_KSEG0_START) && \
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((vm_offset_t)(x) <= MIPS_KSEG0_END))
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#define MIPS_IS_KSEG1_ADDR(x) \
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(((vm_offset_t)(x) >= MIPS_KSEG1_START) && \
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((vm_offset_t)(x) <= MIPS_KSEG1_END))
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#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \
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MIPS_IS_KSEG1_ADDR(x))
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/*
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* Status register.
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*/
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#define SR_COP_USABILITY 0xf0000000
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#define SR_COP_0_BIT 0x10000000
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#define SR_COP_1_BIT 0x20000000
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#define SR_COP_2_BIT 0x40000000
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#define SR_RP 0x08000000
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#define SR_FR_32 0x04000000
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#define SR_RE 0x02000000
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#define SR_PX 0x00800000
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#define SR_BOOT_EXC_VEC 0x00400000
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#define SR_TLB_SHUTDOWN 0x00200000
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#define SR_SOFT_RESET 0x00100000
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#define SR_DIAG_CH 0x00040000
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#define SR_DIAG_CE 0x00020000
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#define SR_DIAG_DE 0x00010000
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#define SR_KX 0x00000080
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#define SR_SX 0x00000040
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#define SR_UX 0x00000020
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#define SR_KSU_MASK 0x00000018
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#define SR_KSU_USER 0x00000010
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#define SR_KSU_SUPER 0x00000008
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#define SR_KSU_KERNEL 0x00000000
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#define SR_ERL 0x00000004
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#define SR_EXL 0x00000002
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#define SR_INT_ENAB 0x00000001
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#define SR_INT_MASK 0x0000ff00
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#define SOFT_INT_MASK_0 0x00000100
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#define SOFT_INT_MASK_1 0x00000200
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#define SR_INT_MASK_0 0x00000400
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#define SR_INT_MASK_1 0x00000800
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#define SR_INT_MASK_2 0x00001000
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#define SR_INT_MASK_3 0x00002000
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#define SR_INT_MASK_4 0x00004000
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#define SR_INT_MASK_5 0x00008000
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#define ALL_INT_MASK SR_INT_MASK
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#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1)
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#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK)
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#define soft_int_mask(softintr) (1 << ((softintr) + 8))
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#define hard_int_mask(hardintr) (1 << ((hardintr) + 10))
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/*
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* The bits in the cause register.
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*
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* CR_BR_DELAY Exception happened in branch delay slot.
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* CR_COP_ERR Coprocessor error.
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* CR_IP Interrupt pending bits defined below.
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* CR_EXC_CODE The exception type (see exception codes below).
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*/
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#define CR_BR_DELAY 0x80000000
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#define CR_COP_ERR 0x30000000
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#define CR_EXC_CODE 0x0000007c
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#define CR_EXC_CODE_SHIFT 2
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#define CR_IPEND 0x0000ff00
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/*
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* Cause Register Format:
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*
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* 31 30 29 28 27 26 25 24 23 8 7 6 2 1 0
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* ----------------------------------------------------------------------
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* | BD | 0| CE | 0| W2| W1| IV| IP15 - IP0 | 0| Exc Code | 0|
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* |______________________________________________________________________
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*/
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#define CR_INT_SOFT0 0x00000100
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#define CR_INT_SOFT1 0x00000200
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#define CR_INT_0 0x00000400
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#define CR_INT_1 0x00000800
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#define CR_INT_2 0x00001000
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#define CR_INT_3 0x00002000
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#define CR_INT_4 0x00004000
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#define CR_INT_5 0x00008000
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#define CR_INT_UART CR_INT_1
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#define CR_INT_IPI CR_INT_2
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#define CR_INT_CLOCK CR_INT_5
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/*
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* The bits in the CONFIG register
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*/
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#define CFG_K0_UNCACHED 2
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#define CFG_K0_CACHED 3
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#define CFG_K0_MASK 0x7
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/*
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* The bits in the context register.
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*/
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#define CNTXT_PTE_BASE 0xff800000
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#define CNTXT_BAD_VPN2 0x007ffff0
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/*
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* Location of exception vectors.
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*/
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#define RESET_EXC_VEC 0xbfc00000
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#define TLB_MISS_EXC_VEC 0x80000000
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#define XTLB_MISS_EXC_VEC 0x80000080
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#define CACHE_ERR_EXC_VEC 0x80000100
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#define GEN_EXC_VEC 0x80000180
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/*
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* Coprocessor 0 registers:
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*/
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#define COP_0_TLB_INDEX $0
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#define COP_0_TLB_RANDOM $1
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#define COP_0_TLB_LO0 $2
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#define COP_0_TLB_LO1 $3
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#define COP_0_TLB_CONTEXT $4
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#define COP_0_TLB_PG_MASK $5
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#define COP_0_TLB_WIRED $6
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#define COP_0_INFO $7
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#define COP_0_BAD_VADDR $8
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#define COP_0_COUNT $9
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#define COP_0_TLB_HI $10
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#define COP_0_COMPARE $11
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#define COP_0_STATUS_REG $12
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#define COP_0_CAUSE_REG $13
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#define COP_0_EXC_PC $14
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#define COP_0_PRID $15
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#define COP_0_CONFIG $16
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#define COP_0_LLADDR $17
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#define COP_0_WATCH_LO $18
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#define COP_0_WATCH_HI $19
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#define COP_0_TLB_XCONTEXT $20
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#define COP_0_ECC $26
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#define COP_0_CACHE_ERR $27
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#define COP_0_TAG_LO $28
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#define COP_0_TAG_HI $29
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#define COP_0_ERROR_PC $30
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/*
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* Coprocessor 0 Set 1
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*/
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#define C0P_1_IPLLO $18
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#define C0P_1_IPLHI $19
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#define C0P_1_INTCTL $20
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#define C0P_1_DERRADDR0 $26
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#define C0P_1_DERRADDR1 $27
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/*
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* Values for the code field in a break instruction.
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*/
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#define BREAK_INSTR 0x0000000d
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#define BREAK_VAL_MASK 0x03ffffc0
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#define BREAK_VAL_SHIFT 16
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#define BREAK_KDB_VAL 512
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#define BREAK_SSTEP_VAL 513
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#define BREAK_BRKPT_VAL 514
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#define BREAK_SOVER_VAL 515
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#define BREAK_DDB_VAL 516
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#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT))
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#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT))
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#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT))
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#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT))
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#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT))
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/*
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* Mininum and maximum cache sizes.
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*/
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#define MIN_CACHE_SIZE (16 * 1024)
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#define MAX_CACHE_SIZE (256 * 1024)
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/*
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* The floating point version and status registers.
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*/
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#define FPC_ID $0
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#define FPC_CSR $31
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/*
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* The floating point coprocessor status register bits.
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*/
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#define FPC_ROUNDING_BITS 0x00000003
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#define FPC_ROUND_RN 0x00000000
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#define FPC_ROUND_RZ 0x00000001
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#define FPC_ROUND_RP 0x00000002
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#define FPC_ROUND_RM 0x00000003
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#define FPC_STICKY_BITS 0x0000007c
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#define FPC_STICKY_INEXACT 0x00000004
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#define FPC_STICKY_UNDERFLOW 0x00000008
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#define FPC_STICKY_OVERFLOW 0x00000010
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#define FPC_STICKY_DIV0 0x00000020
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#define FPC_STICKY_INVALID 0x00000040
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#define FPC_ENABLE_BITS 0x00000f80
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#define FPC_ENABLE_INEXACT 0x00000080
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#define FPC_ENABLE_UNDERFLOW 0x00000100
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#define FPC_ENABLE_OVERFLOW 0x00000200
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#define FPC_ENABLE_DIV0 0x00000400
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#define FPC_ENABLE_INVALID 0x00000800
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#define FPC_EXCEPTION_BITS 0x0003f000
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#define FPC_EXCEPTION_INEXACT 0x00001000
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#define FPC_EXCEPTION_UNDERFLOW 0x00002000
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#define FPC_EXCEPTION_OVERFLOW 0x00004000
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#define FPC_EXCEPTION_DIV0 0x00008000
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#define FPC_EXCEPTION_INVALID 0x00010000
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#define FPC_EXCEPTION_UNIMPL 0x00020000
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#define FPC_COND_BIT 0x00800000
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#define FPC_FLUSH_BIT 0x01000000
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#define FPC_MBZ_BITS 0xfe7c0000
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/*
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* Constants to determine if have a floating point instruction.
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*/
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#define OPCODE_SHIFT 26
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#define OPCODE_C1 0x11
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/*
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* The low part of the TLB entry.
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*/
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#define VMTLB_PF_NUM 0x3fffffc0
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#define VMTLB_ATTR_MASK 0x00000038
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#define VMTLB_MOD_BIT 0x00000004
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#define VMTLB_VALID_BIT 0x00000002
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#define VMTLB_GLOBAL_BIT 0x00000001
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#define VMTLB_PHYS_PAGE_SHIFT 6
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/*
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* The high part of the TLB entry.
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*/
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#define VMTLB_VIRT_PAGE_NUM 0xffffe000
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#define VMTLB_PID 0x000000ff
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#define VMTLB_PID_R9K 0x00000fff
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#define VMTLB_PID_SHIFT 0
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#define VMTLB_VIRT_PAGE_SHIFT 12
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#define VMTLB_VIRT_PAGE_SHIFT_R9K 13
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/*
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* The first TLB entry that write random hits.
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* TLB entry 0 maps the kernel stack of the currently running thread
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* TLB entry 1 maps the pcpu area of processor (only for SMP builds)
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*/
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#define KSTACK_TLB_ENTRY 0
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#ifdef SMP
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#define PCPU_TLB_ENTRY 1
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#define VMWIRED_ENTRIES 2
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#else
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#define VMWIRED_ENTRIES 1
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#endif /* SMP */
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/*
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* The number of process id entries.
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*/
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#define VMNUM_PIDS 256
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/*
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* TLB probe return codes.
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*/
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#define VMTLB_NOT_FOUND 0
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#define VMTLB_FOUND 1
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#define VMTLB_FOUND_WITH_PATCH 2
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#define VMTLB_PROBE_ERROR 3
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/*
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* Exported definitions unique to mips cpu support.
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*/
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define COPY_SIGCODE /* copy sigcode above user stack in exec */
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#define cpu_swapout(p) panic("cpu_swapout: can't get here");
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#ifndef _LOCORE
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#include <machine/frame.h>
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/*
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* Arguments to hardclock and gatherstats encapsulate the previous
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* machine state in an opaque clockframe.
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*/
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#define clockframe trapframe /* Use normal trap frame */
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#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER)
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#define CLKF_BASEPRI(framep) ((framep)->cpl == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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#define CLKF_INTR(framep) (0)
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#define MIPS_CLKF_INTR() (intr_nesting_level >= 1)
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#define TRAPF_USERMODE(framep) (((framep)->sr & SR_KSU_USER) != 0)
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#define TRAPF_PC(framep) ((framep)->pc)
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#define cpu_getstack(td) ((td)->td_frame->sp)
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/*
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* CPU identification, from PRID register.
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*/
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union cpuprid {
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int cpuprid;
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struct {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int pad1:8; /* reserved */
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u_int cp_vendor:8; /* company identifier */
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u_int cp_imp:8; /* implementation identifier */
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u_int cp_majrev:4; /* major revision identifier */
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u_int cp_minrev:4; /* minor revision identifier */
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#else
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u_int cp_minrev:4; /* minor revision identifier */
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u_int cp_majrev:4; /* major revision identifier */
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u_int cp_imp:8; /* implementation identifier */
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u_int cp_vendor:8; /* company identifier */
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u_int pad1:8; /* reserved */
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#endif
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} cpu;
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};
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#endif /* !_LOCORE */
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_ADJKERNTZ 2 /* int: timezone offset (seconds) */
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#define CPU_DISRTCSET 3 /* int: disable resettodr() call */
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#define CPU_BOOTINFO 4 /* struct: bootinfo */
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#define CPU_WALLCLOCK 5 /* int: indicates wall CMOS clock */
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#define CPU_MAXID 6 /* number of valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "console_device", CTLTYPE_STRUCT }, \
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{ "adjkerntz", CTLTYPE_INT }, \
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{ "disable_rtc_set", CTLTYPE_INT }, \
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{ "bootinfo", CTLTYPE_STRUCT }, \
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{ "wall_cmos_clock", CTLTYPE_INT }, \
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}
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/*
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* MIPS CPU types (cp_imp).
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*/
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#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
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#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
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#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
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#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
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#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
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#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
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#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
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#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
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#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
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#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
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#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
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#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
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#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */
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#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */
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#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */
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#define MIPS_RM9000 0x34 /* E9000 CPU */
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/*
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* MIPS FPU types
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*/
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#define MIPS_SOFT 0x00 /* Software emulation ISA I */
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#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
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#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
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#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
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#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
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#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */
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#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
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#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */
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#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */
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#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
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#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */
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#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */
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#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */
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#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */
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#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */
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#ifndef _LOCORE
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extern union cpuprid cpu_id;
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#define mips_proc_type() ((cpu_id.cpu.cp_vendor << 8) | cpu_id.cpu.cp_imp)
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#define mips_set_proc_type(type) (cpu_id.cpu.cp_vendor = (type) >> 8, \
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cpu_id.cpu.cp_imp = ((type) & 0x00ff))
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#endif /* !_LOCORE */
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#if defined(_KERNEL) && !defined(_LOCORE)
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extern union cpuprid fpu_id;
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struct tlb;
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struct user;
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u_int32_t mips_cp0_config1_read(void);
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int Mips_ConfigCache(void);
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void Mips_SetWIRED(int);
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void Mips_SetPID(int);
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u_int Mips_GetCOUNT(void);
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void Mips_SetCOMPARE(u_int);
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u_int Mips_GetCOMPARE(void);
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void Mips_SyncCache(void);
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void Mips_SyncDCache(vm_offset_t, int);
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void Mips_HitSyncDCache(vm_offset_t, int);
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void Mips_HitSyncSCache(vm_offset_t, int);
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void Mips_IOSyncDCache(vm_offset_t, int, int);
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void Mips_HitInvalidateDCache(vm_offset_t, int);
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void Mips_SyncICache(vm_offset_t, int);
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void Mips_InvalidateICache(vm_offset_t, int);
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void Mips_TLBFlush(int);
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void Mips_TLBFlushAddr(vm_offset_t);
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void Mips_TLBWriteIndexed(int, struct tlb *);
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void Mips_TLBUpdate(vm_offset_t, unsigned);
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void Mips_TLBRead(int, struct tlb *);
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void mips_TBIAP(int);
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void wbflush(void);
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extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */
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extern u_int32_t cpu_counter_last; /* Last compare value loaded */
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extern int num_tlbentries;
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extern char btext[];
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extern char etext[];
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extern int intr_nesting_level;
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#define func_0args_asmmacro(func, in) \
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__asm __volatile ( "jalr %0" \
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: "=r" (in) /* outputs */ \
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: "r" (func) /* inputs */ \
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: "$31", "$4");
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#define func_1args_asmmacro(func, arg0) \
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__asm __volatile ("move $4, %1;" \
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"jalr %0" \
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: /* outputs */ \
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: "r" (func), "r" (arg0) /* inputs */ \
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: "$31", "$4");
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#define func_2args_asmmacro(func, arg0, arg1) \
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__asm __volatile ("move $4, %1;" \
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"move $5, %2;" \
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"jalr %0" \
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: /* outputs */ \
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: "r" (func), "r" (arg0), "r" (arg1) /* inputs */ \
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: "$31", "$4", "$5");
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#define func_3args_asmmacro(func, arg0, arg1, arg2) \
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__asm __volatile ( "move $4, %1;" \
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"move $5, %2;" \
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"move $6, %3;" \
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"jalr %0" \
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: /* outputs */ \
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: "r" (func), "r" (arg0), "r" (arg1), "r" (arg2) /* inputs */ \
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: "$31", "$4", "$5", "$6");
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#define MachSetPID Mips_SetPID
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#define MachTLBUpdate Mips_TLBUpdate
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#define mips_TBIS Mips_TLBFlushAddr
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#define MIPS_TBIAP() mips_TBIAP(num_tlbentries)
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#define MachSetWIRED(index) Mips_SetWIRED(index)
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#define MachTLBFlush(count) Mips_TLBFlush(count)
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#define MachTLBGetPID(pid) (pid = Mips_TLBGetPID())
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#define MachTLBRead(tlbno, tlbp) Mips_TLBRead(tlbno, tlbp)
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#define MachFPTrap(sr, cause, pc) MipsFPTrap(sr, cause, pc)
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/*
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* Enable realtime clock (always enabled).
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*/
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#define enablertclock()
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/*
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* Are we in an interrupt handler? required by JunOS
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*/
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#define IN_INT_HANDLER() \
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(curthread->td_intr_nesting_level != 0 || \
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(curthread->td_pflags & TDP_ITHREAD))
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/*
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* Low level access routines to CPU registers
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*/
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void setsoftintr0(void);
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void clearsoftintr0(void);
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void setsoftintr1(void);
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void clearsoftintr1(void);
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u_int32_t mips_cp0_status_read(void);
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void mips_cp0_status_write(u_int32_t);
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int disableintr(void);
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void restoreintr(int);
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int enableintr(void);
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int Mips_TLBGetPID(void);
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void swi_vm(void *);
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void cpu_halt(void);
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void cpu_reset(void);
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u_int32_t set_intr_mask(u_int32_t);
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u_int32_t get_intr_mask(void);
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u_int32_t get_cyclecount(void);
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#define cpu_spinwait() /* nothing */
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#endif /* _KERNEL */
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#endif /* !_MACHINE_CPU_H_ */
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