04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
475 lines
17 KiB
C
475 lines
17 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Support library for the hardware Packet Output unit.
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*
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* <hr>$Revision: 49448 $<hr>
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*/
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-config.h>
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#include <asm/octeon/cvmx-pko.h>
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#include <asm/octeon/cvmx-helper.h>
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#include <asm/octeon/cvmx-clock.h>
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#else
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#if !defined(__FreeBSD__) || !defined(_KERNEL)
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#include "executive-config.h"
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#endif
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#include "cvmx.h"
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#include "cvmx-sysinfo.h"
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#if !defined(__FreeBSD__) || !defined(_KERNEL)
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#include "cvmx-config.h"
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#endif
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#include "cvmx-pko.h"
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#include "cvmx-helper.h"
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#endif
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/**
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* Internal state of packet output
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*/
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#ifdef CVMX_ENABLE_PKO_FUNCTIONS
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/**
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* Call before any other calls to initialize the packet
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* output system. This does chip global config, and should only be
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* done by one core.
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*/
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void cvmx_pko_initialize_global(void)
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{
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int i;
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uint64_t priority = 8;
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cvmx_pko_reg_cmd_buf_t config;
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/* Set the size of the PKO command buffers to an odd number of 64bit
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words. This allows the normal two word send to stay aligned and never
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span a comamnd word buffer. */
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config.u64 = 0;
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config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
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config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1;
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cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
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for (i=0; i<CVMX_PKO_MAX_OUTPUT_QUEUES; i++)
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cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1, &priority);
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/* If we aren't using all of the queues optimize PKO's internal memory */
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if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
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{
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int num_interfaces = cvmx_helper_get_number_of_interfaces();
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int last_port = cvmx_helper_get_last_ipd_port(num_interfaces-1);
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int max_queues = cvmx_pko_get_base_queue(last_port) + cvmx_pko_get_num_queues(last_port);
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if (OCTEON_IS_MODEL(OCTEON_CN38XX))
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{
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if (max_queues <= 32)
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
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else if (max_queues <= 64)
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
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}
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else
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{
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if (max_queues <= 64)
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
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else if (max_queues <= 128)
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
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}
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}
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}
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/**
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* This function does per-core initialization required by the PKO routines.
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* This must be called on all cores that will do packet output, and must
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* be called after the FPA has been initialized and filled with pages.
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*
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* @return 0 on success
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* !0 on failure
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*/
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int cvmx_pko_initialize_local(void)
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{
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/* Nothing to do */
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return 0;
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}
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#endif
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/**
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* Enables the packet output hardware. It must already be
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* configured.
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*/
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void cvmx_pko_enable(void)
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{
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cvmx_pko_reg_flags_t flags;
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flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
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if (flags.s.ena_pko)
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cvmx_dprintf("Warning: Enabling PKO when PKO already enabled.\n");
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flags.s.ena_dwb = 1;
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flags.s.ena_pko = 1;
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flags.s.store_be =1; /* always enable big endian for 3-word command. Does nothing for 2-word */
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cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
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}
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/**
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* Disables the packet output. Does not affect any configuration.
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*/
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void cvmx_pko_disable(void)
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{
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cvmx_pko_reg_flags_t pko_reg_flags;
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pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
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pko_reg_flags.s.ena_pko = 0;
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cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
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}
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#ifdef CVMX_ENABLE_PKO_FUNCTIONS
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/**
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* @INTERNAL
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* Reset the packet output.
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*/
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static void __cvmx_pko_reset(void)
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{
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cvmx_pko_reg_flags_t pko_reg_flags;
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pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
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pko_reg_flags.s.reset = 1;
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cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
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}
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/**
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* Shutdown and free resources required by packet output.
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*/
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void cvmx_pko_shutdown(void)
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{
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cvmx_pko_mem_queue_ptrs_t config;
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int queue;
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cvmx_pko_disable();
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for (queue=0; queue<CVMX_PKO_MAX_OUTPUT_QUEUES; queue++)
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{
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config.u64 = 0;
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config.s.tail = 1;
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config.s.index = 0;
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config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
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config.s.queue = queue & 0x7f;
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config.s.qos_mask = 0;
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config.s.buf_ptr = 0;
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if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
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{
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cvmx_pko_reg_queue_ptrs1_t config1;
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config1.u64 = 0;
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config1.s.qid7 = queue >> 7;
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
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}
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cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
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cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
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}
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__cvmx_pko_reset();
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}
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/**
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* Configure a output port and the associated queues for use.
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*
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* @param port Port to configure.
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* @param base_queue First queue number to associate with this port.
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* @param num_queues Number of queues to associate with this port
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* @param priority Array of priority levels for each queue. Values are
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* allowed to be 0-8. A value of 8 get 8 times the traffic
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* of a value of 1. A value of 0 indicates that no rounds
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* will be participated in. These priorities can be changed
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* on the fly while the pko is enabled. A priority of 9
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* indicates that static priority should be used. If static
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* priority is used all queues with static priority must be
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* contiguous starting at the base_queue, and lower numbered
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* queues have higher priority than higher numbered queues.
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* There must be num_queues elements in the array.
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*/
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cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue, uint64_t num_queues, const uint64_t priority[])
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{
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cvmx_pko_status_t result_code;
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uint64_t queue;
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cvmx_pko_mem_queue_ptrs_t config;
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cvmx_pko_reg_queue_ptrs1_t config1;
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int static_priority_base = -1;
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int static_priority_end = -1;
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if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS) && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID))
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{
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n", (unsigned long long)port);
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return CVMX_PKO_INVALID_PORT;
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}
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if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES)
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{
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n", (unsigned long long)(base_queue + num_queues));
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return CVMX_PKO_INVALID_QUEUE;
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}
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if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)
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{
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/* Validate the static queue priority setup and set static_priority_base and static_priority_end
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** accordingly. */
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for (queue = 0; queue < num_queues; queue++)
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{
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/* Find first queue of static priority */
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if (static_priority_base == -1 && priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
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static_priority_base = queue;
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/* Find last queue of static priority */
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if (static_priority_base != -1 && static_priority_end == -1 && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY && queue)
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static_priority_end = queue - 1;
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else if (static_priority_base != -1 && static_priority_end == -1 && queue == num_queues - 1)
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static_priority_end = queue; /* all queues are static priority */
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/* Check to make sure all static priority queues are contiguous. Also catches some cases of
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** static priorites not starting at queue 0. */
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if (static_priority_end != -1 && (int)queue > static_priority_end && priority[queue] == CVMX_PKO_QUEUE_STATIC_PRIORITY)
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{
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues aren't contiguous or don't start at base queue. q: %d, eq: %d\n", (int)queue, static_priority_end);
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return CVMX_PKO_INVALID_PRIORITY;
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}
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}
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if (static_priority_base > 0)
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{
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Static priority queues don't start at base queue. sq: %d\n", static_priority_base);
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return CVMX_PKO_INVALID_PRIORITY;
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}
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#if 0
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cvmx_dprintf("Port %d: Static priority queue base: %d, end: %d\n", port, static_priority_base, static_priority_end);
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#endif
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}
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/* At this point, static_priority_base and static_priority_end are either both -1,
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** or are valid start/end queue numbers */
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result_code = CVMX_PKO_SUCCESS;
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#ifdef PKO_DEBUG
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cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues, CVMX_PKO_QUEUES_PER_PORT_INTERFACE0, CVMX_PKO_QUEUES_PER_PORT_INTERFACE1);
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#endif
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for (queue = 0; queue < num_queues; queue++)
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{
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uint64_t *buf_ptr = NULL;
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config1.u64 = 0;
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config1.s.idx3 = queue >> 3;
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config1.s.qid7 = (base_queue + queue) >> 7;
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config.u64 = 0;
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config.s.tail = queue == (num_queues - 1);
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config.s.index = queue;
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config.s.port = port;
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config.s.queue = base_queue + queue;
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config.s.static_p = static_priority_base >= 0;
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config.s.static_q = (int)queue <= static_priority_end;
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config.s.s_tail = (int)queue == static_priority_end;
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/* Convert the priority into an enable bit field. Try to space the bits
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out evenly so the packet don't get grouped up */
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switch ((int)priority[queue])
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{
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case 0: config.s.qos_mask = 0x00; break;
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case 1: config.s.qos_mask = 0x01; break;
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case 2: config.s.qos_mask = 0x11; break;
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case 3: config.s.qos_mask = 0x49; break;
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case 4: config.s.qos_mask = 0x55; break;
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case 5: config.s.qos_mask = 0x57; break;
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case 6: config.s.qos_mask = 0x77; break;
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case 7: config.s.qos_mask = 0x7f; break;
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case 8: config.s.qos_mask = 0xff; break;
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case CVMX_PKO_QUEUE_STATIC_PRIORITY:
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config.s.qos_mask = 0xff;
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break;
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default:
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid priority %llu\n", (unsigned long long)priority[queue]);
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config.s.qos_mask = 0xff;
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result_code = CVMX_PKO_INVALID_PRIORITY;
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break;
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}
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if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)
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{
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cvmx_cmd_queue_result_t cmd_res = cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO(base_queue + queue),
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CVMX_PKO_MAX_QUEUE_DEPTH,
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CVMX_FPA_OUTPUT_BUFFER_POOL,
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CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE - CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST*8);
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if (cmd_res != CVMX_CMD_QUEUE_SUCCESS)
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{
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switch (cmd_res)
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{
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case CVMX_CMD_QUEUE_NO_MEMORY:
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Unable to allocate output buffer.\n");
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return(CVMX_PKO_NO_MEMORY);
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case CVMX_CMD_QUEUE_ALREADY_SETUP:
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Port already setup.\n");
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return(CVMX_PKO_PORT_ALREADY_SETUP);
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case CVMX_CMD_QUEUE_INVALID_PARAM:
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default:
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cvmx_dprintf("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n");
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return(CVMX_PKO_CMD_QUEUE_INIT_ERROR);
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}
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}
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buf_ptr = (uint64_t*)cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO(base_queue + queue));
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config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr);
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}
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else
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config.s.buf_ptr = 0;
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CVMX_SYNCWS;
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if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
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{
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cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
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}
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cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
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}
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return result_code;
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}
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#ifdef PKO_DEBUG
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/**
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* Show map of ports -> queues for different cores.
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*/
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void cvmx_pko_show_queue_map()
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{
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int core, port;
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int pko_output_ports = 36;
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cvmx_dprintf("port");
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for(port=0; port<pko_output_ports; port++)
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cvmx_dprintf("%3d ", port);
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cvmx_dprintf("\n");
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for(core=0; core<CVMX_MAX_CORES; core++)
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{
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cvmx_dprintf("\n%2d: ", core);
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for(port=0; port<pko_output_ports; port++)
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{
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cvmx_dprintf("%3d ", cvmx_pko_get_base_queue_per_core(port, core));
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}
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}
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cvmx_dprintf("\n");
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}
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#endif
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/**
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* Rate limit a PKO port to a max packets/sec. This function is only
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* supported on CN51XX and higher, excluding CN58XX.
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*
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* @param port Port to rate limit
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* @param packets_s Maximum packet/sec
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* @param burst Maximum number of packets to burst in a row before rate
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* limiting cuts in.
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*
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* @return Zero on success, negative on failure
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*/
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int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
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{
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cvmx_pko_mem_port_rate0_t pko_mem_port_rate0;
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cvmx_pko_mem_port_rate1_t pko_mem_port_rate1;
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pko_mem_port_rate0.u64 = 0;
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pko_mem_port_rate0.s.pid = port;
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pko_mem_port_rate0.s.rate_pkt = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / packets_s / 16;
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/* No cost per word since we are limited by packets/sec, not bits/sec */
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pko_mem_port_rate0.s.rate_word = 0;
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pko_mem_port_rate1.u64 = 0;
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pko_mem_port_rate1.s.pid = port;
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pko_mem_port_rate1.s.rate_lim = ((uint64_t)pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
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cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
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cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
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return 0;
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}
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|
|
|
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/**
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|
* Rate limit a PKO port to a max bits/sec. This function is only
|
|
* supported on CN51XX and higher, excluding CN58XX.
|
|
*
|
|
* @param port Port to rate limit
|
|
* @param bits_s PKO rate limit in bits/sec
|
|
* @param burst Maximum number of bits to burst before rate
|
|
* limiting cuts in.
|
|
*
|
|
* @return Zero on success, negative on failure
|
|
*/
|
|
int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
|
|
{
|
|
cvmx_pko_mem_port_rate0_t pko_mem_port_rate0;
|
|
cvmx_pko_mem_port_rate1_t pko_mem_port_rate1;
|
|
uint64_t clock_rate = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
|
|
uint64_t tokens_per_bit = clock_rate*16 / bits_s;
|
|
|
|
pko_mem_port_rate0.u64 = 0;
|
|
pko_mem_port_rate0.s.pid = port;
|
|
/* Each packet has a 12 bytes of interframe gap, an 8 byte preamble, and a
|
|
4 byte CRC. These are not included in the per word count. Multiply
|
|
by 8 to covert to bits and divide by 256 for limit granularity */
|
|
pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
|
|
/* Each 8 byte word has 64bits */
|
|
pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit;
|
|
|
|
pko_mem_port_rate1.u64 = 0;
|
|
pko_mem_port_rate1.s.pid = port;
|
|
pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256;
|
|
|
|
cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
|
|
cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
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|
|