Konstantin Belousov 1d1ec02c44 Remove full barrier from the amd64 atomic_load_acq_*(). Strong ... ordering semantic of x86 CPUs makes only the compiler barrier neccessary to give the acquire behaviour. Existing implementation ensured sequentially consistent semantic for load_acq, making much stronger guarantee than required by standard's definition of the load acquire. Consumers which depend on the barrier are believed to be identified and already fixed to use proper operations. Noted by: alc (long time ago) Reviewed by: alc, bde Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 2 weeks		2015-07-28 07:04:51 +00:00
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acpica	If x86 CPU implementation of the MWAIT instruction reasonably	2015-05-09 12:28:48 +00:00
amd64	Various changes to the registers displayed in DDB for x86.	2015-07-22 01:09:02 +00:00
cloudabi64	Make thread creation work for CloudABI processes.	2015-07-21 12:47:15 +00:00
conf	Describe COMPAT_CLOUDABI64 in the amd64 configuration NOTES file.	2015-07-21 12:53:47 +00:00
ia32	Remove several write-only variables, all reported by the gcc 4.9	2015-05-29 13:24:17 +00:00
include	Remove full barrier from the amd64 atomic_load_acq_*(). Strong	2015-07-28 07:04:51 +00:00
linux	Fixup the build after r284215.	2015-06-10 12:39:01 +00:00
linux32	pcb_gs32sd is unused for long time, remove it. Keep the padding in pcb.	2015-06-29 07:53:44 +00:00
pci	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
vmm	Move the 'devmem' device nodes from /dev/vmm to /dev/vmm.io	2015-07-06 19:41:43 +00:00
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