4ad7e9b01a
SoCs and various chips (including, famously, their wifi chips.) This is "just" (all 20,000 lines of it) code to enumerate the various versions of busses inside these devices, including the PCI bridge and the direct SIBA bridge found in MIPS chips. It also includes shared code for some bus operations (suspend, resume, etc); EEPROM/SROM/etc parsing and other things that are shared between chips. Eventually this'll replace the code that bwi/bwn uses for the internal bus, as well as some apparently upcoming mips74k broadcom SoC support which uses bwn! Thanks to Landon Fuller <landonf@landonf.org> for all this work! Obtained from: https://github.com/landonf/freebsd/compare/user/landonf/bcm4331-CURRENT
78 lines
3.3 KiB
C
78 lines
3.3 KiB
C
/*-
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* Copyright (c) 2015 Landon Fuller <landon@landonf.org>
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* Copyright (c) 2010 Broadcom Corporation
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*
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* This file is derived from the hndsoc.h header distributed with
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* Broadcom's initial brcm80211 Linux driver release, as
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* contributed to the Linux staging repository.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _BHND_BHND_CORE_H_
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#define _BHND_BHND_CORE_H_
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/* Common core control flags */
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#define BHND_CF_BIST_EN 0x8000 /**< ??? */
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#define BHND_CF_PME_EN 0x4000 /**< ??? */
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#define BHND_CF_CORE_BITS 0x3ffc /**< core specific flag mask */
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#define BHND_CF_FGC 0x0002 /**< force clock gating */
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#define BHND_CF_CLOCK_EN 0x0001 /**< enable clock */
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/* Common core status flags */
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#define BHND_SF_BIST_DONE 0x8000 /**< ??? */
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#define BHND_SF_BIST_ERROR 0x4000 /**< ??? */
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#define BHND_SF_GATED_CLK 0x2000 /**< clock gated */
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#define BHND_SF_DMA64 0x1000 /**< supports 64-bit DMA */
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#define BHND_SF_CORE_BITS 0x0fff /**< core-specific status mask */
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/*
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* A register that is common to all cores to
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* communicate w/PMU regarding clock control.
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*
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* TODO: Determine when this register first appeared.
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*/
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#define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
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/*
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* BHND_CLK_CTL_ST register
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*
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* Clock Mode Name Description
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* High Throughput (HT) Full bandwidth, low latency. Generally supplied
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* from PLL.
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* Active Low Power (ALP) Register access, low speed DMA.
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* Idle Low Power (ILP) No interconnect activity, or if long latency
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* is permitted.
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*/
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#define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
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#define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
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#define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
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#define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
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#define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
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#define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */
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#define BHND_CCS_ERSRC_REQ_MASK 0x00000700 /**< external resource requests */
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#define BHND_CCS_ERSRC_REQ_SHIFT 8
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#define BHND_CCS_ALPAVAIL 0x00010000 /**< ALP is available */
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#define BHND_CCS_HTAVAIL 0x00020000 /**< HT is available */
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#define BHND_CCS_BP_ON_APL 0x00040000 /**< RO: Backplane is running on ALP clock */
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#define BHND_CCS_BP_ON_HT 0x00080000 /**< RO: Backplane is running on HT clock */
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#define BHND_CCS_ERSRC_STS_MASK 0x07000000 /**< external resource status */
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#define BHND_CCS_ERSRC_STS_SHIFT 24
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#define BHND_CCS0_HTAVAIL 0x00010000 /**< HT avail in chipc and pcmcia on 4328a0 */
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#define BHND_CCS0_ALPAVAIL 0x00020000 /**< ALP avail in chipc and pcmcia on 4328a0 */
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#endif /* _BHND_BHND_CORE_H_ */
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