695 lines
16 KiB
C
695 lines
16 KiB
C
/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
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/*-
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* Copyright (C) 2003-2004 Olivier Houchard
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* Copyright (C) 1994-1997 Mark Brinicombe
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* Copyright (C) 1994 Brini
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of Brini may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_V6_H_
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#define _MACHINE_ATOMIC_V6_H_
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#ifndef _MACHINE_ATOMIC_H_
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#error Do not include this file directly, use <machine/atomic.h>
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#endif
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#if __ARM_ARCH >= 7
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#define isb() __asm __volatile("isb" : : : "memory")
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#define dsb() __asm __volatile("dsb" : : : "memory")
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#define dmb() __asm __volatile("dmb" : : : "memory")
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#elif __ARM_ARCH >= 6
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#define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory")
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#define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
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#define dmb() __asm __volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory")
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#else
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#error Only use this file with ARMv6 and later
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#endif
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#define mb() dmb()
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#define wmb() dmb()
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#define rmb() dmb()
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#define ARM_HAVE_ATOMIC64
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#define ATOMIC_ACQ_REL_LONG(NAME) \
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static __inline void \
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atomic_##NAME##_acq_long(__volatile u_long *p, u_long v) \
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{ \
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atomic_##NAME##_long(p, v); \
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dmb(); \
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} \
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\
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static __inline void \
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atomic_##NAME##_rel_long(__volatile u_long *p, u_long v) \
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{ \
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dmb(); \
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atomic_##NAME##_long(p, v); \
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}
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#define ATOMIC_ACQ_REL(NAME, WIDTH) \
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static __inline void \
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atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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{ \
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atomic_##NAME##_##WIDTH(p, v); \
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dmb(); \
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} \
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\
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static __inline void \
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atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
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{ \
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dmb(); \
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atomic_##NAME##_##WIDTH(p, v); \
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}
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static __inline void
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atomic_add_32(volatile uint32_t *p, uint32_t val)
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{
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uint32_t tmp = 0, tmp2 = 0;
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__asm __volatile(
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"1: ldrex %0, [%2] \n"
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" add %0, %0, %3 \n"
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" strex %1, %0, [%2] \n"
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" cmp %1, #0 \n"
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" it ne \n"
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" bne 1b \n"
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: "=&r" (tmp), "+r" (tmp2)
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,"+r" (p), "+r" (val) : : "cc", "memory");
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}
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static __inline void
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atomic_add_64(volatile uint64_t *p, uint64_t val)
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{
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uint64_t tmp;
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uint32_t exflag;
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__asm __volatile(
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"1: \n"
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" ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n"
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" adds %Q[tmp], %Q[val] \n"
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" adc %R[tmp], %R[tmp], %R[val] \n"
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" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n"
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" teq %[exf], #0 \n"
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" it ne \n"
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" bne 1b \n"
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: [exf] "=&r" (exflag),
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[tmp] "=&r" (tmp)
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: [ptr] "r" (p),
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[val] "r" (val)
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: "cc", "memory");
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}
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static __inline void
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atomic_add_long(volatile u_long *p, u_long val)
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{
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atomic_add_32((volatile uint32_t *)p, val);
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}
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ATOMIC_ACQ_REL(add, 32)
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ATOMIC_ACQ_REL(add, 64)
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ATOMIC_ACQ_REL_LONG(add)
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static __inline void
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atomic_clear_32(volatile uint32_t *address, uint32_t setmask)
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{
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uint32_t tmp = 0, tmp2 = 0;
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__asm __volatile(
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"1: ldrex %0, [%2] \n"
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" bic %0, %0, %3 \n"
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" strex %1, %0, [%2] \n"
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" cmp %1, #0 \n"
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" it ne \n"
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" bne 1b \n"
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: "=&r" (tmp), "+r" (tmp2), "+r" (address), "+r" (setmask)
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: : "cc", "memory");
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}
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static __inline void
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atomic_clear_64(volatile uint64_t *p, uint64_t val)
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{
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uint64_t tmp;
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uint32_t exflag;
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__asm __volatile(
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"1: \n"
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" ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n"
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" bic %Q[tmp], %Q[val] \n"
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" bic %R[tmp], %R[val] \n"
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" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n"
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" teq %[exf], #0 \n"
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" it ne \n"
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" bne 1b \n"
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: [exf] "=&r" (exflag),
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[tmp] "=&r" (tmp)
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: [ptr] "r" (p),
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[val] "r" (val)
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: "cc", "memory");
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}
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static __inline void
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atomic_clear_long(volatile u_long *address, u_long setmask)
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{
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atomic_clear_32((volatile uint32_t *)address, setmask);
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}
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ATOMIC_ACQ_REL(clear, 32)
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ATOMIC_ACQ_REL(clear, 64)
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ATOMIC_ACQ_REL_LONG(clear)
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static __inline uint32_t
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atomic_cmpset_32(volatile uint32_t *p, uint32_t cmpval, uint32_t newval)
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{
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uint32_t ret;
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__asm __volatile(
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"1: ldrex %0, [%1] \n"
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" cmp %0, %2 \n"
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" itt ne \n"
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" movne %0, #0 \n"
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" bne 2f \n"
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" strex %0, %3, [%1] \n"
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" cmp %0, #0 \n"
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" ite eq \n"
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" moveq %0, #1 \n"
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" bne 1b \n"
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"2:"
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: "=&r" (ret), "+r" (p), "+r" (cmpval), "+r" (newval)
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: : "cc", "memory");
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return (ret);
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}
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static __inline int
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atomic_cmpset_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
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{
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uint64_t tmp;
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uint32_t ret;
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__asm __volatile(
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"1: \n"
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" ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n"
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" teq %Q[tmp], %Q[cmpval] \n"
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" itee eq \n"
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" teqeq %R[tmp], %R[cmpval] \n"
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" movne %[ret], #0 \n"
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" bne 2f \n"
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" strexd %[ret], %Q[newval], %R[newval], [%[ptr]]\n"
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" teq %[ret], #0 \n"
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" it ne \n"
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" bne 1b \n"
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" mov %[ret], #1 \n"
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"2: \n"
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: [ret] "=&r" (ret),
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[tmp] "=&r" (tmp)
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: [ptr] "r" (p),
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[cmpval] "r" (cmpval),
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[newval] "r" (newval)
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: "cc", "memory");
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return (ret);
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}
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static __inline u_long
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atomic_cmpset_long(volatile u_long *p, u_long cmpval, u_long newval)
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{
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return (atomic_cmpset_32((volatile uint32_t *)p, cmpval, newval));
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}
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static __inline uint32_t
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atomic_cmpset_acq_32(volatile uint32_t *p, uint32_t cmpval, uint32_t newval)
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{
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uint32_t ret;
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ret = atomic_cmpset_32(p, cmpval, newval);
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dmb();
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return (ret);
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}
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static __inline uint64_t
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atomic_cmpset_acq_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
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{
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uint64_t ret;
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ret = atomic_cmpset_64(p, cmpval, newval);
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dmb();
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return (ret);
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}
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static __inline u_long
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atomic_cmpset_acq_long(volatile u_long *p, u_long cmpval, u_long newval)
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{
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u_long ret;
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ret = atomic_cmpset_long(p, cmpval, newval);
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dmb();
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return (ret);
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}
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static __inline uint32_t
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atomic_cmpset_rel_32(volatile uint32_t *p, uint32_t cmpval, uint32_t newval)
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{
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dmb();
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return (atomic_cmpset_32(p, cmpval, newval));
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}
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static __inline uint64_t
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atomic_cmpset_rel_64(volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
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{
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dmb();
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return (atomic_cmpset_64(p, cmpval, newval));
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}
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static __inline u_long
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atomic_cmpset_rel_long(volatile u_long *p, u_long cmpval, u_long newval)
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{
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dmb();
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return (atomic_cmpset_long(p, cmpval, newval));
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}
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static __inline uint32_t
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atomic_fetchadd_32(volatile uint32_t *p, uint32_t val)
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{
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uint32_t tmp = 0, tmp2 = 0, ret = 0;
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__asm __volatile(
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"1: ldrex %0, [%3] \n"
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" add %1, %0, %4 \n"
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" strex %2, %1, [%3] \n"
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" cmp %2, #0 \n"
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" it ne \n"
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" bne 1b \n"
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: "+r" (ret), "=&r" (tmp), "+r" (tmp2), "+r" (p), "+r" (val)
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: : "cc", "memory");
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return (ret);
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}
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static __inline uint64_t
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atomic_fetchadd_64(volatile uint64_t *p, uint64_t val)
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{
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uint64_t ret, tmp;
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uint32_t exflag;
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__asm __volatile(
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"1: \n"
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" ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n"
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" adds %Q[tmp], %Q[ret], %Q[val] \n"
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" adc %R[tmp], %R[ret], %R[val] \n"
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" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n"
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" teq %[exf], #0 \n"
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" it ne \n"
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" bne 1b \n"
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: [ret] "=&r" (ret),
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[exf] "=&r" (exflag),
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[tmp] "=&r" (tmp)
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: [ptr] "r" (p),
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[val] "r" (val)
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: "cc", "memory");
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return (ret);
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}
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static __inline u_long
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atomic_fetchadd_long(volatile u_long *p, u_long val)
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{
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return (atomic_fetchadd_32((volatile uint32_t *)p, val));
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}
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static __inline uint32_t
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atomic_load_acq_32(volatile uint32_t *p)
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{
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uint32_t v;
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v = *p;
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dmb();
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return (v);
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}
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static __inline uint64_t
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atomic_load_64(volatile uint64_t *p)
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{
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uint64_t ret;
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/*
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* The only way to atomically load 64 bits is with LDREXD which puts the
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* exclusive monitor into the exclusive state, so reset it to open state
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* with CLREX because we don't actually need to store anything.
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*/
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__asm __volatile(
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"ldrexd %Q[ret], %R[ret], [%[ptr]] \n"
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"clrex \n"
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: [ret] "=&r" (ret)
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: [ptr] "r" (p)
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: "cc", "memory");
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return (ret);
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}
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static __inline uint64_t
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atomic_load_acq_64(volatile uint64_t *p)
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{
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uint64_t ret;
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ret = atomic_load_64(p);
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dmb();
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return (ret);
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}
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static __inline u_long
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atomic_load_acq_long(volatile u_long *p)
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{
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u_long v;
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v = *p;
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dmb();
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return (v);
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}
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static __inline uint32_t
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atomic_readandclear_32(volatile uint32_t *p)
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{
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uint32_t ret, tmp = 0, tmp2 = 0;
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__asm __volatile(
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"1: ldrex %0, [%3] \n"
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" mov %1, #0 \n"
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" strex %2, %1, [%3] \n"
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" cmp %2, #0 \n"
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" it ne \n"
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" bne 1b \n"
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: "=r" (ret), "=&r" (tmp), "+r" (tmp2), "+r" (p)
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: : "cc", "memory");
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return (ret);
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}
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static __inline uint64_t
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atomic_readandclear_64(volatile uint64_t *p)
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{
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uint64_t ret, tmp;
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uint32_t exflag;
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__asm __volatile(
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"1: \n"
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" ldrexd %Q[ret], %R[ret], [%[ptr]] \n"
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" mov %Q[tmp], #0 \n"
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" mov %R[tmp], #0 \n"
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" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n"
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" teq %[exf], #0 \n"
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" it ne \n"
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" bne 1b \n"
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: [ret] "=&r" (ret),
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[exf] "=&r" (exflag),
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[tmp] "=&r" (tmp)
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: [ptr] "r" (p)
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: "cc", "memory");
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return (ret);
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}
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static __inline u_long
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atomic_readandclear_long(volatile u_long *p)
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{
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return (atomic_readandclear_32((volatile uint32_t *)p));
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}
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static __inline void
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atomic_set_32(volatile uint32_t *address, uint32_t setmask)
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{
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uint32_t tmp = 0, tmp2 = 0;
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__asm __volatile(
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"1: ldrex %0, [%2] \n"
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" orr %0, %0, %3 \n"
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" strex %1, %0, [%2] \n"
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" cmp %1, #0 \n"
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" it ne \n"
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" bne 1b \n"
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: "=&r" (tmp), "+r" (tmp2), "+r" (address), "+r" (setmask)
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: : "cc", "memory");
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}
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static __inline void
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atomic_set_64(volatile uint64_t *p, uint64_t val)
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{
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uint64_t tmp;
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uint32_t exflag;
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__asm __volatile(
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"1: \n"
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" ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n"
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" orr %Q[tmp], %Q[val] \n"
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" orr %R[tmp], %R[val] \n"
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" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n"
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" teq %[exf], #0 \n"
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" it ne \n"
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" bne 1b \n"
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: [exf] "=&r" (exflag),
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[tmp] "=&r" (tmp)
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: [ptr] "r" (p),
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[val] "r" (val)
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: "cc", "memory");
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}
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static __inline void
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atomic_set_long(volatile u_long *address, u_long setmask)
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{
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atomic_set_32((volatile uint32_t *)address, setmask);
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}
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ATOMIC_ACQ_REL(set, 32)
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ATOMIC_ACQ_REL(set, 64)
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ATOMIC_ACQ_REL_LONG(set)
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|
|
static __inline void
|
|
atomic_subtract_32(volatile uint32_t *p, uint32_t val)
|
|
{
|
|
uint32_t tmp = 0, tmp2 = 0;
|
|
|
|
__asm __volatile(
|
|
"1: ldrex %0, [%2] \n"
|
|
" sub %0, %0, %3 \n"
|
|
" strex %1, %0, [%2] \n"
|
|
" cmp %1, #0 \n"
|
|
" it ne \n"
|
|
" bne 1b \n"
|
|
: "=&r" (tmp), "+r" (tmp2), "+r" (p), "+r" (val)
|
|
: : "cc", "memory");
|
|
}
|
|
|
|
static __inline void
|
|
atomic_subtract_64(volatile uint64_t *p, uint64_t val)
|
|
{
|
|
uint64_t tmp;
|
|
uint32_t exflag;
|
|
|
|
__asm __volatile(
|
|
"1: \n"
|
|
" ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n"
|
|
" subs %Q[tmp], %Q[val] \n"
|
|
" sbc %R[tmp], %R[tmp], %R[val] \n"
|
|
" strexd %[exf], %Q[tmp], %R[tmp], [%[ptr]] \n"
|
|
" teq %[exf], #0 \n"
|
|
" it ne \n"
|
|
" bne 1b \n"
|
|
: [exf] "=&r" (exflag),
|
|
[tmp] "=&r" (tmp)
|
|
: [ptr] "r" (p),
|
|
[val] "r" (val)
|
|
: "cc", "memory");
|
|
}
|
|
|
|
static __inline void
|
|
atomic_subtract_long(volatile u_long *p, u_long val)
|
|
{
|
|
|
|
atomic_subtract_32((volatile uint32_t *)p, val);
|
|
}
|
|
|
|
ATOMIC_ACQ_REL(subtract, 32)
|
|
ATOMIC_ACQ_REL(subtract, 64)
|
|
ATOMIC_ACQ_REL_LONG(subtract)
|
|
|
|
static __inline void
|
|
atomic_store_64(volatile uint64_t *p, uint64_t val)
|
|
{
|
|
uint64_t tmp;
|
|
uint32_t exflag;
|
|
|
|
/*
|
|
* The only way to atomically store 64 bits is with STREXD, which will
|
|
* succeed only if paired up with a preceeding LDREXD using the same
|
|
* address, so we read and discard the existing value before storing.
|
|
*/
|
|
__asm __volatile(
|
|
"1: \n"
|
|
" ldrexd %Q[tmp], %R[tmp], [%[ptr]] \n"
|
|
" strexd %[exf], %Q[val], %R[val], [%[ptr]] \n"
|
|
" teq %[exf], #0 \n"
|
|
" it ne \n"
|
|
" bne 1b \n"
|
|
: [tmp] "=&r" (tmp),
|
|
[exf] "=&r" (exflag)
|
|
: [ptr] "r" (p),
|
|
[val] "r" (val)
|
|
: "cc", "memory");
|
|
}
|
|
|
|
static __inline void
|
|
atomic_store_rel_32(volatile uint32_t *p, uint32_t v)
|
|
{
|
|
|
|
dmb();
|
|
*p = v;
|
|
}
|
|
|
|
static __inline void
|
|
atomic_store_rel_64(volatile uint64_t *p, uint64_t val)
|
|
{
|
|
|
|
dmb();
|
|
atomic_store_64(p, val);
|
|
}
|
|
|
|
static __inline void
|
|
atomic_store_rel_long(volatile u_long *p, u_long v)
|
|
{
|
|
|
|
dmb();
|
|
*p = v;
|
|
}
|
|
|
|
static __inline int
|
|
atomic_testandset_32(volatile uint32_t *p, u_int v)
|
|
{
|
|
uint32_t tmp, tmp2, res, mask;
|
|
|
|
mask = 1u << (v & 0x1f);
|
|
tmp = tmp2 = 0;
|
|
__asm __volatile(
|
|
"1: ldrex %0, [%4] \n"
|
|
" orr %1, %0, %3 \n"
|
|
" strex %2, %1, [%4] \n"
|
|
" cmp %2, #0 \n"
|
|
" it ne \n"
|
|
" bne 1b \n"
|
|
: "=&r" (res), "=&r" (tmp), "=&r" (tmp2)
|
|
: "r" (mask), "r" (p)
|
|
: "cc", "memory");
|
|
return ((res & mask) != 0);
|
|
}
|
|
|
|
static __inline int
|
|
atomic_testandset_int(volatile u_int *p, u_int v)
|
|
{
|
|
|
|
return (atomic_testandset_32((volatile uint32_t *)p, v));
|
|
}
|
|
|
|
static __inline int
|
|
atomic_testandset_long(volatile u_long *p, u_int v)
|
|
{
|
|
|
|
return (atomic_testandset_32((volatile uint32_t *)p, v));
|
|
}
|
|
|
|
static __inline int
|
|
atomic_testandset_64(volatile uint64_t *p, u_int v)
|
|
{
|
|
volatile uint32_t *p32;
|
|
|
|
p32 = (volatile uint32_t *)p;
|
|
/* Assume little-endian */
|
|
if (v >= 32) {
|
|
v &= 0x1f;
|
|
p32++;
|
|
}
|
|
return (atomic_testandset_32(p32, v));
|
|
}
|
|
|
|
static __inline uint32_t
|
|
atomic_swap_32(volatile uint32_t *p, uint32_t v)
|
|
{
|
|
uint32_t ret, exflag;
|
|
|
|
__asm __volatile(
|
|
"1: ldrex %[ret], [%[ptr]] \n"
|
|
" strex %[exf], %[val], [%[ptr]] \n"
|
|
" teq %[exf], #0 \n"
|
|
" it ne \n"
|
|
" bne 1b \n"
|
|
: [ret] "=r" (ret),
|
|
[exf] "=&r" (exflag)
|
|
: [val] "r" (v),
|
|
[ptr] "r" (p)
|
|
: "cc", "memory");
|
|
return (ret);
|
|
}
|
|
|
|
#undef ATOMIC_ACQ_REL
|
|
#undef ATOMIC_ACQ_REL_LONG
|
|
|
|
static __inline void
|
|
atomic_thread_fence_acq(void)
|
|
{
|
|
|
|
dmb();
|
|
}
|
|
|
|
static __inline void
|
|
atomic_thread_fence_rel(void)
|
|
{
|
|
|
|
dmb();
|
|
}
|
|
|
|
static __inline void
|
|
atomic_thread_fence_acq_rel(void)
|
|
{
|
|
|
|
dmb();
|
|
}
|
|
|
|
static __inline void
|
|
atomic_thread_fence_seq_cst(void)
|
|
{
|
|
|
|
dmb();
|
|
}
|
|
|
|
#endif /* _MACHINE_ATOMIC_V6_H_ */
|