1ebcad5720
not work on any real hardware (or fully work on any simulator). Much more needs to happen before this is actually functional but its nice to see the FreeBSD copyright message appear in the ia64 simulator.
191 lines
5.6 KiB
C
191 lines
5.6 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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/*
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* Various simple arithmetic on memory which is atomic in the presence
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* of interrupts and SMP safe.
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*/
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/*
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* Everything is built out of cmpxchg.
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*/
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#define IA64_CMPXCHG(sz, sem, type, p, cmpval, newval) \
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({ \
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type _cmpval = cmpval; \
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type _newval = newval; \
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volatile type *_p = (volatile type *) p; \
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type _ret; \
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\
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__asm __volatile ( \
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"mov ar.ccv=%2;;\n\t" \
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"cmpxchg" #sz "." #sem " %0=%4,%3,ar.ccv\n\t" \
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: "=r" (_ret), "=m" (*_p) \
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: "r" (_cmpval), "r" (_newval), "m" (*_p) \
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: "memory"); \
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_ret; \
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})
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/*
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* Some common forms of cmpxch.
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*/
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static __inline u_int32_t
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ia64_cmpxchg_acq_32(volatile u_int32_t* p, u_int32_t cmpval, u_int32_t newval)
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{
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return IA64_CMPXCHG(4, acq, u_int32_t, p, cmpval, newval);
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}
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static __inline u_int32_t
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ia64_cmpxchg_rel_32(volatile u_int32_t* p, u_int32_t cmpval, u_int32_t newval)
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{
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return IA64_CMPXCHG(4, rel, u_int32_t, p, cmpval, newval);
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}
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static __inline u_int64_t
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ia64_cmpxchg_acq_64(volatile u_int64_t* p, u_int64_t cmpval, u_int64_t newval)
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{
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return IA64_CMPXCHG(8, acq, u_int64_t, p, cmpval, newval);
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}
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static __inline u_int64_t
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ia64_cmpxchg_rel_64(volatile u_int64_t* p, u_int64_t cmpval, u_int64_t newval)
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{
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return IA64_CMPXCHG(8, rel, u_int64_t, p, cmpval, newval);
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}
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/*
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* Store with release semantics is used to release locks.
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*/
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static __inline void
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ia64_st_rel_32(volatile u_int32_t* p, u_int32_t v)
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{
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__asm __volatile ("st4.rel %0=%1"
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: "=m" (*p)
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: "r" (v)
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: "memory");
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}
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static __inline void
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ia64_st_rel_64(volatile u_int64_t* p, u_int64_t v)
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{
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__asm __volatile ("st8.rel %0=%1"
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: "=m" (*p)
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: "r" (v)
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: "memory");
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}
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#define IA64_ATOMIC(sz, type, name, op) \
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\
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static __inline void \
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atomic_##name(volatile type *p, type v) \
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{ \
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type old; \
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do { \
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old = *p; \
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} while (IA64_CMPXCHG(sz, acq, type, p, old, old op v) != old); \
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}
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IA64_ATOMIC(1, u_int8_t, set_8, |)
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IA64_ATOMIC(2, u_int16_t, set_16, |)
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IA64_ATOMIC(4, u_int32_t, set_32, |)
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IA64_ATOMIC(8, u_int64_t, set_64, |)
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IA64_ATOMIC(1, u_int8_t, clear_8, &~)
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IA64_ATOMIC(2, u_int16_t, clear_16, &~)
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IA64_ATOMIC(4, u_int32_t, clear_32, &~)
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IA64_ATOMIC(8, u_int64_t, clear_64, &~)
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IA64_ATOMIC(1, u_int8_t, add_8, +)
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IA64_ATOMIC(2, u_int16_t, add_16, +)
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IA64_ATOMIC(4, u_int32_t, add_32, +)
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IA64_ATOMIC(8, u_int64_t, add_64, +)
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IA64_ATOMIC(1, u_int8_t, subtract_8, -)
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IA64_ATOMIC(2, u_int16_t, subtract_16, -)
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IA64_ATOMIC(4, u_int32_t, subtract_32, -)
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IA64_ATOMIC(8, u_int64_t, subtract_64, -)
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#undef IA64_ATOMIC
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#undef IA64_CMPXCHG
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#define atomic_set_char atomic_set_8
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#define atomic_clear_char atomic_clear_8
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#define atomic_add_char atomic_add_8
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#define atomic_subtract_char atomic_subtract_8
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#define atomic_set_short atomic_set_16
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#define atomic_clear_short atomic_clear_16
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#define atomic_add_short atomic_add_16
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#define atomic_subtract_short atomic_subtract_16
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#define atomic_set_int atomic_set_32
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#define atomic_clear_int atomic_clear_32
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#define atomic_add_int atomic_add_32
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#define atomic_subtract_int atomic_subtract_32
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#define atomic_set_long atomic_set_64
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#define atomic_clear_long atomic_clear_64
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#define atomic_add_long atomic_add_64
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#define atomic_subtract_long atomic_subtract_64
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/*
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* Atomically compare the value stored at *p with cmpval and if the
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* two values are equal, update the value of *p with newval. Returns
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* zero if the compare failed, nonzero otherwise.
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*/
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static __inline int
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atomic_cmpset_32(volatile u_int32_t* p, u_int32_t cmpval, u_int32_t newval)
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{
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return ia64_cmpxchg_acq_32(p, cmpval, newval) == cmpval;
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}
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/*
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* Atomically compare the value stored at *p with cmpval and if the
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* two values are equal, update the value of *p with newval. Returns
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* zero if the compare failed, nonzero otherwise.
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*/
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static __inline int
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atomic_cmpset_64(volatile u_int64_t* p, u_int64_t cmpval, u_int64_t newval)
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{
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return ia64_cmpxchg_acq_64(p, cmpval, newval) == cmpval;
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}
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#define atomic_cmpset_int atomic_cmpset_32
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#define atomic_cmpset_long atomic_cmpset_64
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static __inline int
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atomic_cmpset_ptr(volatile void *dst, void *exp, void *src)
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{
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return atomic_cmpset_long((volatile u_long *)dst,
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(u_long)exp, (u_long)src);
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}
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#endif /* ! _MACHINE_ATOMIC_H_ */
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