af3dc4a7ca
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
459 lines
11 KiB
C
459 lines
11 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Clocks and power control driver for Freescale i.MX6 family of SoCs.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <arm/freescale/imx/imx6_anatopreg.h>
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#include <arm/freescale/imx/imx6_anatopvar.h>
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#include <arm/freescale/imx/imx6_ccmreg.h>
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#include <arm/freescale/imx/imx_machdep.h>
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#include <arm/freescale/imx/imx_ccmvar.h>
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#ifndef CCGR_CLK_MODE_ALWAYS
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#define CCGR_CLK_MODE_OFF 0
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#define CCGR_CLK_MODE_RUNMODE 1
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#define CCGR_CLK_MODE_ALWAYS 3
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#endif
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struct ccm_softc {
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device_t dev;
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struct resource *mem_res;
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};
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static struct ccm_softc *ccm_sc;
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static inline uint32_t
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RD4(struct ccm_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->mem_res, off));
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}
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static inline void
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WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off, val);
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}
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/*
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* Until we have a fully functional ccm driver which implements the fdt_clock
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* interface, use the age-old workaround of unconditionally enabling the clocks
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* for devices we might need to use. The SoC defaults to most clocks enabled,
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* but the rom boot code and u-boot disable a few of them. We turn on only
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* what's needed to run the chip plus devices we have drivers for, and turn off
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* devices we don't yet have drivers for. (Note that USB is not turned on here
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* because that is one we do when the driver asks for it.)
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*/
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static void
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ccm_init_gates(struct ccm_softc *sc)
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{
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uint32_t reg;
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/* ahpbdma, aipstz 1 & 2 buses */
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reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA;
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WR4(sc, CCM_CCGR0, reg);
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/* enet, epit, gpt */
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reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT;
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WR4(sc, CCM_CCGR1, reg);
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/* ipmux & ipsync (bridges), iomux, i2c */
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reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM |
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CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 |
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CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 |
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CCGR2_IPSYNC_VDOA;
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WR4(sc, CCM_CCGR2, reg);
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/* DDR memory controller */
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reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG |
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CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13;
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WR4(sc, CCM_CCGR3, reg);
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/* pl301 bus crossbar */
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reg = CCGR4_PL301_MX6QFAST1_S133 |
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CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN;
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WR4(sc, CCM_CCGR4, reg);
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/* uarts, ssi, sdma */
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reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 |
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CCGR5_UART | CCGR5_UART_SERIAL;
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WR4(sc, CCM_CCGR5, reg);
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/* usdhc 1-4, usboh3 */
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reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 |
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CCGR6_USDHC3 | CCGR6_USDHC4;
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WR4(sc, CCM_CCGR6, reg);
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}
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static int
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ccm_detach(device_t dev)
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{
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struct ccm_softc *sc;
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sc = device_get_softc(dev);
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
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return (0);
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}
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static int
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ccm_attach(device_t dev)
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{
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struct ccm_softc *sc;
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int err, rid;
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uint32_t reg;
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sc = device_get_softc(dev);
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err = 0;
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/* Allocate bus_space resources. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Cannot allocate memory resources\n");
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err = ENXIO;
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goto out;
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}
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ccm_sc = sc;
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/*
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* Configure the Low Power Mode setting to leave the ARM core power on
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* when a WFI instruction is executed. This lets the MPCore timers and
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* GIC continue to run, which is helpful when the only thing that can
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* wake you up is an MPCore Private Timer interrupt delivered via GIC.
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*
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* XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be
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* required when the LPM bits are set to LPM_RUN. But experimentally
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* I've experienced a fairly rare lockup when not setting it. I was
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* unable to prove conclusively that the lockup was related to power
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* management or that this definitively fixes it. Revisit this.
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*/
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reg = RD4(sc, CCM_CGPR);
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reg |= CCM_CGPR_INT_MEM_CLK_LPM;
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WR4(sc, CCM_CGPR, reg);
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reg = RD4(sc, CCM_CLPCR);
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reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN;
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WR4(sc, CCM_CLPCR, reg);
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ccm_init_gates(sc);
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err = 0;
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out:
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if (err != 0)
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ccm_detach(dev);
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return (err);
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}
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static int
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ccm_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0)
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return (ENXIO);
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device_set_desc(dev, "Freescale i.MX6 Clock Control Module");
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return (BUS_PROBE_DEFAULT);
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}
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void
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imx_ccm_ssi_configure(device_t _ssidev)
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{
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struct ccm_softc *sc;
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uint32_t reg;
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sc = ccm_sc;
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/*
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* Select PLL4 (Audio PLL) clock multiplexer as source.
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* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM).
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*/
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reg = RD4(sc, CCM_CSCMR1);
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reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S);
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reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S);
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reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S);
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reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S);
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reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S);
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reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S);
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WR4(sc, CCM_CSCMR1, reg);
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/*
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* Ensure we have set hardware-default values
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* for pre and post dividers.
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*/
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/* SSI1 and SSI3 */
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reg = RD4(sc, CCM_CS1CDR);
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/* Divide by 2 */
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reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT);
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reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT);
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reg |= (0x1 << SSI1_CLK_PODF_SHIFT);
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reg |= (0x1 << SSI3_CLK_PODF_SHIFT);
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/* Divide by 4 */
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reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT);
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reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT);
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reg |= (0x3 << SSI1_CLK_PRED_SHIFT);
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reg |= (0x3 << SSI3_CLK_PRED_SHIFT);
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WR4(sc, CCM_CS1CDR, reg);
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/* SSI2 */
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reg = RD4(sc, CCM_CS2CDR);
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/* Divide by 2 */
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reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT);
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reg |= (0x1 << SSI2_CLK_PODF_SHIFT);
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/* Divide by 4 */
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reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT);
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reg |= (0x3 << SSI2_CLK_PRED_SHIFT);
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WR4(sc, CCM_CS2CDR, reg);
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}
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void
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imx_ccm_usb_enable(device_t _usbdev)
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{
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/*
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* For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for
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* shifting and masking here, just set the low-order two bits to ALWAYS.
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*/
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WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS);
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}
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void
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imx_ccm_usbphy_enable(device_t _phydev)
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{
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/*
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* XXX Which unit?
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* Right now it's not clear how to figure from fdt data which phy unit
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* we're supposed to operate on. Until this is worked out, just enable
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* both PHYs.
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*/
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#if 0
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int phy_num, regoff;
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phy_num = 0; /* XXX */
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switch (phy_num) {
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case 0:
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regoff = 0;
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break;
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case 1:
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regoff = 0x10;
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break;
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default:
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device_printf(ccm_sc->dev, "Bad PHY number %u,\n",
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phy_num);
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return;
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}
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imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff,
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IMX6_ANALOG_CCM_PLL_USB_ENABLE |
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IMX6_ANALOG_CCM_PLL_USB_POWER |
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IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
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#else
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imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0,
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IMX6_ANALOG_CCM_PLL_USB_ENABLE |
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IMX6_ANALOG_CCM_PLL_USB_POWER |
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IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
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imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10,
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IMX6_ANALOG_CCM_PLL_USB_ENABLE |
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IMX6_ANALOG_CCM_PLL_USB_POWER |
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IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
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#endif
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}
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int
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imx6_ccm_sata_enable(void)
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{
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uint32_t v;
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int timeout;
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/* Un-gate the sata controller. */
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WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA);
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/* Power up the PLL that feeds ENET/SATA/PCI phys, wait for lock. */
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v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET);
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v &= ~CCM_ANALOG_PLL_ENET_POWERDOWN;
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WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
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for (timeout = 100000; timeout > 0; timeout--) {
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if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) &
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CCM_ANALOG_PLL_ENET_LOCK) {
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break;
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}
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}
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if (timeout <= 0) {
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return ETIMEDOUT;
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}
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/* Enable the PLL, and enable its 100mhz output. */
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v |= CCM_ANALOG_PLL_ENET_ENABLE;
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v &= ~CCM_ANALOG_PLL_ENET_BYPASS;
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WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
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v |= CCM_ANALOG_PLL_ENET_ENABLE_100M;
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WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
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return 0;
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}
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uint32_t
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imx_ccm_ipg_hz(void)
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{
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return (66000000);
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}
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uint32_t
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imx_ccm_perclk_hz(void)
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{
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return (66000000);
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}
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uint32_t
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imx_ccm_sdhci_hz(void)
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{
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return (200000000);
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}
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uint32_t
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imx_ccm_uart_hz(void)
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{
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return (80000000);
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}
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uint32_t
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imx_ccm_ahb_hz(void)
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{
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return (132000000);
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}
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void
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imx_ccm_ipu_enable(int ipu)
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{
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struct ccm_softc *sc;
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uint32_t reg;
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sc = ccm_sc;
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reg = RD4(sc, CCM_CCGR3);
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if (ipu == 1)
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reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0;
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else
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reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0;
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WR4(sc, CCM_CCGR3, reg);
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}
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void
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imx_ccm_hdmi_enable(void)
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{
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struct ccm_softc *sc;
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uint32_t reg;
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sc = ccm_sc;
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reg = RD4(sc, CCM_CCGR2);
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reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR;
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WR4(sc, CCM_CCGR2, reg);
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/* Set HDMI clock to 280MHz */
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reg = RD4(sc, CCM_CHSCCDR);
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reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
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CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);
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reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);
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WR4(sc, CCM_CHSCCDR, reg);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);
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WR4(sc, CCM_CHSCCDR, reg);
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}
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uint32_t
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imx_ccm_get_cacrr(void)
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{
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return (RD4(ccm_sc, CCM_CACCR));
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}
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void
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imx_ccm_set_cacrr(uint32_t divisor)
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{
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WR4(ccm_sc, CCM_CACCR, divisor);
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}
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static device_method_t ccm_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ccm_probe),
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DEVMETHOD(device_attach, ccm_attach),
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DEVMETHOD(device_detach, ccm_detach),
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DEVMETHOD_END
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};
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static driver_t ccm_driver = {
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"ccm",
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ccm_methods,
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sizeof(struct ccm_softc)
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};
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static devclass_t ccm_devclass;
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EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0,
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BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
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