As cs is stored in a uint32_t, use the last bit to store the active high flag as it's unlikely that we will have that much CS. Reviewed by: loos MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D8614
294 lines
8.2 KiB
C
294 lines
8.2 KiB
C
/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Vybrid Family Serial Peripheral Interface (SPI)
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* Chapter 47, Vybrid Reference Manual, Rev. 5, 07/2013
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include "spibus_if.h"
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/freescale/vybrid/vf_common.h>
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#define SPI_FIFO_SIZE 4
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#define SPI_MCR 0x00 /* Module Configuration */
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#define MCR_MSTR (1 << 31) /* Master/Slave Mode Select */
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#define MCR_CONT_SCKE (1 << 30) /* Continuous SCK Enable */
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#define MCR_FRZ (1 << 27) /* Freeze */
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#define MCR_PCSIS_S 16 /* Peripheral Chip Select */
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#define MCR_PCSIS_M 0x3f
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#define MCR_MDIS (1 << 14) /* Module Disable */
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#define MCR_CLR_TXF (1 << 11) /* Clear TX FIFO */
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#define MCR_CLR_RXF (1 << 10) /* Clear RX FIFO */
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#define MCR_HALT (1 << 0) /* Starts and stops SPI transfers */
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#define SPI_TCR 0x08 /* Transfer Count */
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#define SPI_CTAR0 0x0C /* Clock and Transfer Attributes */
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#define SPI_CTAR0_SLAVE 0x0C /* Clock and Transfer Attributes */
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#define SPI_CTAR1 0x10 /* Clock and Transfer Attributes */
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#define SPI_CTAR2 0x14 /* Clock and Transfer Attributes */
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#define SPI_CTAR3 0x18 /* Clock and Transfer Attributes */
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#define CTAR_FMSZ_M 0xf
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#define CTAR_FMSZ_S 27 /* Frame Size */
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#define CTAR_FMSZ_8 0x7 /* 8 bits */
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#define CTAR_CPOL (1 << 26) /* Clock Polarity */
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#define CTAR_CPHA (1 << 25) /* Clock Phase */
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#define CTAR_LSBFE (1 << 24) /* Less significant bit first */
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#define CTAR_PCSSCK_M 0x3
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#define CTAR_PCSSCK_S 22 /* PCS to SCK Delay Prescaler */
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#define CTAR_PBR_M 0x3
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#define CTAR_PBR_S 16 /* Baud Rate Prescaler */
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#define CTAR_PBR_7 0x3 /* Divide by 7 */
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#define CTAR_CSSCK_M 0xf
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#define CTAR_CSSCK_S 12 /* PCS to SCK Delay Scaler */
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#define CTAR_BR_M 0xf
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#define CTAR_BR_S 0 /* Baud Rate Scaler */
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#define SPI_SR 0x2C /* Status Register */
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#define SR_TCF (1 << 31) /* Transfer Complete Flag */
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#define SR_EOQF (1 << 28) /* End of Queue Flag */
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#define SR_TFFF (1 << 25) /* Transmit FIFO Fill Flag */
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#define SR_RFDF (1 << 17) /* Receive FIFO Drain Flag */
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#define SPI_RSER 0x30 /* DMA/Interrupt Select */
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#define RSER_EOQF_RE (1 << 28) /* Finished Request Enable */
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#define SPI_PUSHR 0x34 /* PUSH TX FIFO In Master Mode */
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#define PUSHR_CONT (1 << 31) /* Continuous Peripheral CS */
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#define PUSHR_EOQ (1 << 27) /* End Of Queue */
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#define PUSHR_CTCNT (1 << 26) /* Clear Transfer Counter */
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#define PUSHR_PCS_M 0x3f
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#define PUSHR_PCS_S 16 /* Select PCS signals */
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#define SPI_PUSHR_SLAVE 0x34 /* PUSH TX FIFO Register In Slave Mode */
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#define SPI_POPR 0x38 /* POP RX FIFO Register */
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#define SPI_TXFR0 0x3C /* Transmit FIFO Registers */
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#define SPI_TXFR1 0x40
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#define SPI_TXFR2 0x44
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#define SPI_TXFR3 0x48
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#define SPI_RXFR0 0x7C /* Receive FIFO Registers */
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#define SPI_RXFR1 0x80
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#define SPI_RXFR2 0x84
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#define SPI_RXFR3 0x88
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struct spi_softc {
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struct resource *res[2];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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void *ih;
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};
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static struct resource_spec spi_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int
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spi_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "fsl,mvf600-spi"))
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return (ENXIO);
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device_set_desc(dev, "Vybrid Family Serial Peripheral Interface");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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spi_attach(device_t dev)
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{
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struct spi_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, spi_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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reg = READ4(sc, SPI_MCR);
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reg |= MCR_MSTR;
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reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ);
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reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S);
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reg |= (MCR_PCSIS_M << MCR_PCSIS_S); /* PCS Active low */
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reg |= (MCR_CLR_TXF | MCR_CLR_RXF);
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WRITE4(sc, SPI_MCR, reg);
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reg = READ4(sc, SPI_RSER);
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reg |= RSER_EOQF_RE;
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WRITE4(sc, SPI_RSER, reg);
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reg = READ4(sc, SPI_MCR);
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reg &= ~MCR_HALT;
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WRITE4(sc, SPI_MCR, reg);
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reg = READ4(sc, SPI_CTAR0);
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reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S);
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reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S);
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/*
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* TODO: calculate BR
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* SCK baud rate = ( fsys / PBR ) * (1 + DBR) / BR
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*
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* reg &= ~(CTAR_BR_M << CTAR_BR_S);
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*/
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reg &= ~CTAR_CPOL; /* Polarity */
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reg |= CTAR_CPHA;
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/*
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* Set LSB (Less significant bit first)
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* must be used for some applications, e.g. some LCDs
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*/
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reg |= CTAR_LSBFE;
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WRITE4(sc, SPI_CTAR0, reg);
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reg = READ4(sc, SPI_CTAR0);
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reg &= ~(CTAR_PBR_M << CTAR_PBR_S);
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reg |= (CTAR_PBR_7 << CTAR_PBR_S);
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WRITE4(sc, SPI_CTAR0, reg);
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device_add_child(dev, "spibus", 0);
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return (bus_generic_attach(dev));
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}
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static int
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spi_txrx(struct spi_softc *sc, uint8_t *out_buf,
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uint8_t *in_buf, int bufsz, int cs)
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{
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uint32_t reg, wreg;
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uint32_t txcnt;
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uint32_t i;
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txcnt = 0;
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for (i = 0; i < bufsz; i++) {
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txcnt++;
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wreg = out_buf[i];
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wreg |= PUSHR_CONT;
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wreg |= (cs << PUSHR_PCS_S);
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if (i == 0)
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wreg |= PUSHR_CTCNT;
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if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE)
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wreg |= PUSHR_EOQ;
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WRITE4(sc, SPI_PUSHR, wreg);
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if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) {
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txcnt = 0;
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/* Wait last entry in a queue to be transmitted */
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while((READ4(sc, SPI_SR) & SR_EOQF) == 0)
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continue;
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reg = READ4(sc, SPI_SR);
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reg |= (SR_TCF | SR_EOQF);
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WRITE4(sc, SPI_SR, reg);
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}
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/* Wait until RX FIFO is empty */
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while((READ4(sc, SPI_SR) & SR_RFDF) == 0)
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continue;
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in_buf[i] = READ1(sc, SPI_POPR);
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}
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return (0);
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}
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static int
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spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct spi_softc *sc;
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uint32_t cs;
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sc = device_get_softc(dev);
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KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
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("%s: TX/RX command sizes should be equal", __func__));
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KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
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("%s: TX/RX data sizes should be equal", __func__));
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/* get the proper chip select */
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spibus_get_cs(child, &cs);
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cs &= ~SPIBUS_CS_HIGH;
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/* Command */
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spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs);
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/* Data */
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spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs);
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return (0);
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}
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static device_method_t spi_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, spi_probe),
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DEVMETHOD(device_attach, spi_attach),
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/* SPI interface */
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DEVMETHOD(spibus_transfer, spi_transfer),
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{ 0, 0 }
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};
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static driver_t spi_driver = {
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"spi",
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spi_methods,
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sizeof(struct spi_softc),
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};
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static devclass_t spi_devclass;
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DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0);
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