719 lines
19 KiB
C
719 lines
19 KiB
C
/*-
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* Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/limits.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "pwmbus_if.h"
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#include "am335x_pwm.h"
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/*******************************************************************************
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* Enhanced resolution PWM driver. Many of the advanced featues of the hardware
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* are not supported by this driver. What is implemented here is simple
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* variable-duty-cycle PWM output.
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*
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* Note that this driver was historically configured using a set of sysctl
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* variables/procs, and later gained support for the PWM(9) API. The sysctl
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* code is still present to support existing apps, but that interface is
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* considered deprecated.
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*
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* An important caveat is that the original sysctl interface and the new PWM API
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* cannot both be used at once. If both interfaces are used to change
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* configuration, it's quite likely you won't get the expected results. Also,
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* reading the sysctl values after configuring via PWM will not return the right
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* results.
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******************************************************************************/
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/* In ticks */
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#define DEFAULT_PWM_PERIOD 1000
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#define PWM_CLOCK 100000000UL
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#define NS_PER_SEC 1000000000
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#define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define PWM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \
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device_get_nameunit(_sc->sc_dev), "am335x_ehrpwm softc", MTX_DEF)
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#define PWM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#define EPWM_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg)
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#define EPWM_WRITE2(_sc, reg, value) \
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bus_write_2((_sc)->sc_mem_res, reg, value)
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#define EPWM_TBCTL 0x00
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#define TBCTL_FREERUN (2 << 14)
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#define TBCTL_PHDIR_UP (1 << 13)
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#define TBCTL_PHDIR_DOWN (0 << 13)
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#define TBCTL_CLKDIV(x) ((x) << 10)
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#define TBCTL_CLKDIV_MASK (3 << 10)
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#define TBCTL_HSPCLKDIV(x) ((x) << 7)
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#define TBCTL_HSPCLKDIV_MASK (3 << 7)
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#define TBCTL_SYNCOSEL_DISABLED (3 << 4)
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#define TBCTL_PRDLD_SHADOW (0 << 3)
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#define TBCTL_PRDLD_IMMEDIATE (0 << 3)
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#define TBCTL_PHSEN_ENABLED (1 << 2)
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#define TBCTL_PHSEN_DISABLED (0 << 2)
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#define TBCTL_CTRMODE_MASK (3)
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#define TBCTL_CTRMODE_UP (0 << 0)
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#define TBCTL_CTRMODE_DOWN (1 << 0)
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#define TBCTL_CTRMODE_UPDOWN (2 << 0)
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#define TBCTL_CTRMODE_FREEZE (3 << 0)
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#define EPWM_TBSTS 0x02
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#define EPWM_TBPHSHR 0x04
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#define EPWM_TBPHS 0x06
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#define EPWM_TBCNT 0x08
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#define EPWM_TBPRD 0x0a
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/* Counter-compare */
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#define EPWM_CMPCTL 0x0e
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#define CMPCTL_SHDWBMODE_SHADOW (1 << 6)
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#define CMPCTL_SHDWBMODE_IMMEDIATE (0 << 6)
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#define CMPCTL_SHDWAMODE_SHADOW (1 << 4)
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#define CMPCTL_SHDWAMODE_IMMEDIATE (0 << 4)
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#define CMPCTL_LOADBMODE_ZERO (0 << 2)
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#define CMPCTL_LOADBMODE_PRD (1 << 2)
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#define CMPCTL_LOADBMODE_EITHER (2 << 2)
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#define CMPCTL_LOADBMODE_FREEZE (3 << 2)
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#define CMPCTL_LOADAMODE_ZERO (0 << 0)
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#define CMPCTL_LOADAMODE_PRD (1 << 0)
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#define CMPCTL_LOADAMODE_EITHER (2 << 0)
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#define CMPCTL_LOADAMODE_FREEZE (3 << 0)
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#define EPWM_CMPAHR 0x10
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#define EPWM_CMPA 0x12
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#define EPWM_CMPB 0x14
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/* CMPCTL_LOADAMODE_ZERO */
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#define EPWM_AQCTLA 0x16
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#define EPWM_AQCTLB 0x18
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#define AQCTL_CBU_NONE (0 << 8)
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#define AQCTL_CBU_CLEAR (1 << 8)
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#define AQCTL_CBU_SET (2 << 8)
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#define AQCTL_CBU_TOGGLE (3 << 8)
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#define AQCTL_CAU_NONE (0 << 4)
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#define AQCTL_CAU_CLEAR (1 << 4)
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#define AQCTL_CAU_SET (2 << 4)
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#define AQCTL_CAU_TOGGLE (3 << 4)
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#define AQCTL_ZRO_NONE (0 << 0)
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#define AQCTL_ZRO_CLEAR (1 << 0)
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#define AQCTL_ZRO_SET (2 << 0)
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#define AQCTL_ZRO_TOGGLE (3 << 0)
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#define EPWM_AQSFRC 0x1a
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#define EPWM_AQCSFRC 0x1c
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#define AQCSFRC_OFF 0
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#define AQCSFRC_LO 1
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#define AQCSFRC_HI 2
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#define AQCSFRC_MASK 3
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#define AQCSFRC(chan, hilo) ((hilo) << (2 * chan))
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/* Trip-Zone module */
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#define EPWM_TZCTL 0x28
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#define EPWM_TZFLG 0x2C
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/* High-Resolution PWM */
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#define EPWM_HRCTL 0x40
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#define HRCTL_DELMODE_BOTH 3
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#define HRCTL_DELMODE_FALL 2
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#define HRCTL_DELMODE_RISE 1
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static device_probe_t am335x_ehrpwm_probe;
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static device_attach_t am335x_ehrpwm_attach;
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static device_detach_t am335x_ehrpwm_detach;
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static int am335x_ehrpwm_clkdiv[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
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struct ehrpwm_channel {
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u_int duty; /* on duration, in ns */
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bool enabled; /* channel enabled? */
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bool inverted; /* signal inverted? */
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};
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#define NUM_CHANNELS 2
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struct am335x_ehrpwm_softc {
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device_t sc_dev;
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device_t sc_busdev;
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struct mtx sc_mtx;
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struct resource *sc_mem_res;
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int sc_mem_rid;
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/* Things used for configuration via sysctl [deprecated]. */
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int sc_pwm_clkdiv;
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int sc_pwm_freq;
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struct sysctl_oid *sc_clkdiv_oid;
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struct sysctl_oid *sc_freq_oid;
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struct sysctl_oid *sc_period_oid;
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struct sysctl_oid *sc_chanA_oid;
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struct sysctl_oid *sc_chanB_oid;
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uint32_t sc_pwm_period;
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uint32_t sc_pwm_dutyA;
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uint32_t sc_pwm_dutyB;
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/* Things used for configuration via pwm(9) api. */
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u_int sc_clkfreq; /* frequency in Hz */
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u_int sc_clktick; /* duration in ns */
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u_int sc_period; /* duration in ns */
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struct ehrpwm_channel sc_channels[NUM_CHANNELS];
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};
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static struct ofw_compat_data compat_data[] = {
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{"ti,am33xx-ehrpwm", true},
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{NULL, false},
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};
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SIMPLEBUS_PNP_INFO(compat_data);
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static void
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am335x_ehrpwm_cfg_duty(struct am335x_ehrpwm_softc *sc, u_int chan, u_int duty)
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{
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u_int tbcmp;
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if (duty == 0)
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tbcmp = 0;
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else
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tbcmp = max(1, duty / sc->sc_clktick);
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sc->sc_channels[chan].duty = tbcmp * sc->sc_clktick;
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PWM_LOCK_ASSERT(sc);
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EPWM_WRITE2(sc, (chan == 0) ? EPWM_CMPA : EPWM_CMPB, tbcmp);
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}
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static void
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am335x_ehrpwm_cfg_enable(struct am335x_ehrpwm_softc *sc, u_int chan, bool enable)
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{
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uint16_t regval;
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sc->sc_channels[chan].enabled = enable;
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/*
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* Turn off any existing software-force of the channel, then force
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* it in the right direction (high or low) if it's not being enabled.
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*/
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PWM_LOCK_ASSERT(sc);
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regval = EPWM_READ2(sc, EPWM_AQCSFRC);
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regval &= ~AQCSFRC(chan, AQCSFRC_MASK);
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if (!sc->sc_channels[chan].enabled) {
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if (sc->sc_channels[chan].inverted)
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regval |= AQCSFRC(chan, AQCSFRC_HI);
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else
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regval |= AQCSFRC(chan, AQCSFRC_LO);
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}
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EPWM_WRITE2(sc, EPWM_AQCSFRC, regval);
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}
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static bool
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am335x_ehrpwm_cfg_period(struct am335x_ehrpwm_softc *sc, u_int period)
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{
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uint16_t regval;
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u_int clkdiv, hspclkdiv, pwmclk, pwmtick, tbprd;
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/* Can't do a period shorter than 2 clock ticks. */
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if (period < 2 * NS_PER_SEC / PWM_CLOCK) {
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sc->sc_clkfreq = 0;
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sc->sc_clktick = 0;
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sc->sc_period = 0;
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return (false);
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}
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/*
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* Figure out how much we have to divide down the base 100MHz clock so
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* that we can express the requested period as a 16-bit tick count.
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*/
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tbprd = 0;
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for (clkdiv = 0; clkdiv < 8; ++clkdiv) {
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const u_int cd = 1 << clkdiv;
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for (hspclkdiv = 0; hspclkdiv < 8; ++hspclkdiv) {
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const u_int cdhs = max(1, hspclkdiv * 2);
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pwmclk = PWM_CLOCK / (cd * cdhs);
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pwmtick = NS_PER_SEC / pwmclk;
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if (period / pwmtick < 65536) {
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tbprd = period / pwmtick;
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break;
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}
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}
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if (tbprd != 0)
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break;
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}
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/* Handle requested period too long for available clock divisors. */
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if (tbprd == 0)
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return (false);
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/*
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* If anything has changed from the current settings, reprogram the
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* clock divisors and period register.
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*/
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if (sc->sc_clkfreq != pwmclk || sc->sc_clktick != pwmtick ||
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sc->sc_period != tbprd * pwmtick) {
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sc->sc_clkfreq = pwmclk;
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sc->sc_clktick = pwmtick;
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sc->sc_period = tbprd * pwmtick;
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PWM_LOCK_ASSERT(sc);
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regval = EPWM_READ2(sc, EPWM_TBCTL);
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regval &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);
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regval |= TBCTL_CLKDIV(clkdiv) | TBCTL_HSPCLKDIV(hspclkdiv);
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EPWM_WRITE2(sc, EPWM_TBCTL, regval);
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EPWM_WRITE2(sc, EPWM_TBPRD, tbprd - 1);
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#if 0
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device_printf(sc->sc_dev, "clkdiv %u hspclkdiv %u tbprd %u "
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"clkfreq %u Hz clktick %u ns period got %u requested %u\n",
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clkdiv, hspclkdiv, tbprd - 1,
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sc->sc_clkfreq, sc->sc_clktick, sc->sc_period, period);
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#endif
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/*
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* If the period changed, that invalidates the current CMP
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* registers (duty values), just zero them out.
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*/
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am335x_ehrpwm_cfg_duty(sc, 0, 0);
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am335x_ehrpwm_cfg_duty(sc, 1, 0);
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}
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return (true);
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}
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static void
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am335x_ehrpwm_freq(struct am335x_ehrpwm_softc *sc)
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{
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int clkdiv;
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clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv];
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sc->sc_pwm_freq = PWM_CLOCK / (1 * clkdiv) / sc->sc_pwm_period;
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}
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static int
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am335x_ehrpwm_sysctl_freq(SYSCTL_HANDLER_ARGS)
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{
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int clkdiv, error, freq, i, period;
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struct am335x_ehrpwm_softc *sc;
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uint32_t reg;
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sc = (struct am335x_ehrpwm_softc *)arg1;
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PWM_LOCK(sc);
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freq = sc->sc_pwm_freq;
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PWM_UNLOCK(sc);
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error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (freq > PWM_CLOCK)
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freq = PWM_CLOCK;
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PWM_LOCK(sc);
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if (freq != sc->sc_pwm_freq) {
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for (i = nitems(am335x_ehrpwm_clkdiv) - 1; i >= 0; i--) {
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clkdiv = am335x_ehrpwm_clkdiv[i];
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period = PWM_CLOCK / clkdiv / freq;
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if (period > USHRT_MAX)
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break;
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sc->sc_pwm_clkdiv = i;
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sc->sc_pwm_period = period;
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}
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/* Reset the duty cycle settings. */
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sc->sc_pwm_dutyA = 0;
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sc->sc_pwm_dutyB = 0;
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EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
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EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
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/* Update the clkdiv settings. */
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reg = EPWM_READ2(sc, EPWM_TBCTL);
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reg &= ~TBCTL_CLKDIV_MASK;
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reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv);
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EPWM_WRITE2(sc, EPWM_TBCTL, reg);
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/* Update the period settings. */
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EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1);
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am335x_ehrpwm_freq(sc);
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}
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PWM_UNLOCK(sc);
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return (0);
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}
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static int
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am335x_ehrpwm_sysctl_clkdiv(SYSCTL_HANDLER_ARGS)
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{
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int error, i, clkdiv;
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struct am335x_ehrpwm_softc *sc;
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uint32_t reg;
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sc = (struct am335x_ehrpwm_softc *)arg1;
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PWM_LOCK(sc);
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clkdiv = am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv];
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PWM_UNLOCK(sc);
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error = sysctl_handle_int(oidp, &clkdiv, sizeof(clkdiv), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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PWM_LOCK(sc);
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if (clkdiv != am335x_ehrpwm_clkdiv[sc->sc_pwm_clkdiv]) {
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for (i = 0; i < nitems(am335x_ehrpwm_clkdiv); i++)
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if (clkdiv >= am335x_ehrpwm_clkdiv[i])
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sc->sc_pwm_clkdiv = i;
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reg = EPWM_READ2(sc, EPWM_TBCTL);
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reg &= ~TBCTL_CLKDIV_MASK;
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reg |= TBCTL_CLKDIV(sc->sc_pwm_clkdiv);
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EPWM_WRITE2(sc, EPWM_TBCTL, reg);
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am335x_ehrpwm_freq(sc);
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}
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PWM_UNLOCK(sc);
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return (0);
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}
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static int
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am335x_ehrpwm_sysctl_duty(SYSCTL_HANDLER_ARGS)
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{
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struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1;
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int error;
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uint32_t duty;
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if (oidp == sc->sc_chanA_oid)
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duty = sc->sc_pwm_dutyA;
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else
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duty = sc->sc_pwm_dutyB;
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error = sysctl_handle_int(oidp, &duty, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (duty > sc->sc_pwm_period) {
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device_printf(sc->sc_dev, "Duty cycle can't be greater then period\n");
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return (EINVAL);
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}
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PWM_LOCK(sc);
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if (oidp == sc->sc_chanA_oid) {
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sc->sc_pwm_dutyA = duty;
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EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
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}
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else {
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sc->sc_pwm_dutyB = duty;
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EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
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}
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PWM_UNLOCK(sc);
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return (error);
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}
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static int
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am335x_ehrpwm_sysctl_period(SYSCTL_HANDLER_ARGS)
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{
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struct am335x_ehrpwm_softc *sc = (struct am335x_ehrpwm_softc*)arg1;
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int error;
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uint32_t period;
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|
period = sc->sc_pwm_period;
|
|
error = sysctl_handle_int(oidp, &period, 0, req);
|
|
|
|
if (error != 0 || req->newptr == NULL)
|
|
return (error);
|
|
|
|
if (period < 1)
|
|
return (EINVAL);
|
|
|
|
if (period > USHRT_MAX)
|
|
period = USHRT_MAX;
|
|
|
|
PWM_LOCK(sc);
|
|
/* Reset the duty cycle settings. */
|
|
sc->sc_pwm_dutyA = 0;
|
|
sc->sc_pwm_dutyB = 0;
|
|
EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
|
|
EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
|
|
/* Update the period settings. */
|
|
sc->sc_pwm_period = period;
|
|
EPWM_WRITE2(sc, EPWM_TBPRD, period - 1);
|
|
am335x_ehrpwm_freq(sc);
|
|
PWM_UNLOCK(sc);
|
|
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
am335x_ehrpwm_channel_count(device_t dev, u_int *nchannel)
|
|
{
|
|
|
|
*nchannel = NUM_CHANNELS;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
am335x_ehrpwm_channel_config(device_t dev, u_int channel, u_int period, u_int duty)
|
|
{
|
|
struct am335x_ehrpwm_softc *sc;
|
|
bool status;
|
|
|
|
if (channel >= NUM_CHANNELS)
|
|
return (EINVAL);
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
PWM_LOCK(sc);
|
|
status = am335x_ehrpwm_cfg_period(sc, period);
|
|
if (status)
|
|
am335x_ehrpwm_cfg_duty(sc, channel, duty);
|
|
PWM_UNLOCK(sc);
|
|
|
|
return (status ? 0 : EINVAL);
|
|
}
|
|
|
|
static int
|
|
am335x_ehrpwm_channel_get_config(device_t dev, u_int channel,
|
|
u_int *period, u_int *duty)
|
|
{
|
|
struct am335x_ehrpwm_softc *sc;
|
|
|
|
if (channel >= NUM_CHANNELS)
|
|
return (EINVAL);
|
|
|
|
sc = device_get_softc(dev);
|
|
*period = sc->sc_period;
|
|
*duty = sc->sc_channels[channel].duty;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
am335x_ehrpwm_channel_enable(device_t dev, u_int channel, bool enable)
|
|
{
|
|
struct am335x_ehrpwm_softc *sc;
|
|
|
|
if (channel >= NUM_CHANNELS)
|
|
return (EINVAL);
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
PWM_LOCK(sc);
|
|
am335x_ehrpwm_cfg_enable(sc, channel, enable);
|
|
PWM_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
am335x_ehrpwm_channel_is_enabled(device_t dev, u_int channel, bool *enabled)
|
|
{
|
|
struct am335x_ehrpwm_softc *sc;
|
|
|
|
if (channel >= NUM_CHANNELS)
|
|
return (EINVAL);
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
*enabled = sc->sc_channels[channel].enabled;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
am335x_ehrpwm_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "AM335x EHRPWM");
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
am335x_ehrpwm_attach(device_t dev)
|
|
{
|
|
struct am335x_ehrpwm_softc *sc;
|
|
uint32_t reg;
|
|
struct sysctl_ctx_list *ctx;
|
|
struct sysctl_oid *tree;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->sc_dev = dev;
|
|
|
|
PWM_LOCK_INIT(sc);
|
|
|
|
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&sc->sc_mem_rid, RF_ACTIVE);
|
|
if (sc->sc_mem_res == NULL) {
|
|
device_printf(dev, "cannot allocate memory resources\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Init sysctl interface */
|
|
ctx = device_get_sysctl_ctx(sc->sc_dev);
|
|
tree = device_get_sysctl_tree(sc->sc_dev);
|
|
|
|
sc->sc_clkdiv_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
|
|
"clkdiv", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
|
|
am335x_ehrpwm_sysctl_clkdiv, "I", "PWM clock prescaler");
|
|
|
|
sc->sc_freq_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
|
|
"freq", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
|
|
am335x_ehrpwm_sysctl_freq, "I", "PWM frequency");
|
|
|
|
sc->sc_period_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
|
|
"period", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
|
|
am335x_ehrpwm_sysctl_period, "I", "PWM period");
|
|
|
|
sc->sc_chanA_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
|
|
"dutyA", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
|
|
am335x_ehrpwm_sysctl_duty, "I", "Channel A duty cycles");
|
|
|
|
sc->sc_chanB_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
|
|
"dutyB", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
|
|
am335x_ehrpwm_sysctl_duty, "I", "Channel B duty cycles");
|
|
|
|
/* CONFIGURE EPWM1 */
|
|
reg = EPWM_READ2(sc, EPWM_TBCTL);
|
|
reg &= ~(TBCTL_CLKDIV_MASK | TBCTL_HSPCLKDIV_MASK);
|
|
EPWM_WRITE2(sc, EPWM_TBCTL, reg);
|
|
|
|
sc->sc_pwm_period = DEFAULT_PWM_PERIOD;
|
|
sc->sc_pwm_dutyA = 0;
|
|
sc->sc_pwm_dutyB = 0;
|
|
am335x_ehrpwm_freq(sc);
|
|
|
|
EPWM_WRITE2(sc, EPWM_TBPRD, sc->sc_pwm_period - 1);
|
|
EPWM_WRITE2(sc, EPWM_CMPA, sc->sc_pwm_dutyA);
|
|
EPWM_WRITE2(sc, EPWM_CMPB, sc->sc_pwm_dutyB);
|
|
|
|
EPWM_WRITE2(sc, EPWM_AQCTLA, (AQCTL_ZRO_SET | AQCTL_CAU_CLEAR));
|
|
EPWM_WRITE2(sc, EPWM_AQCTLB, (AQCTL_ZRO_SET | AQCTL_CBU_CLEAR));
|
|
|
|
/* START EPWM */
|
|
reg &= ~TBCTL_CTRMODE_MASK;
|
|
reg |= TBCTL_CTRMODE_UP | TBCTL_FREERUN;
|
|
EPWM_WRITE2(sc, EPWM_TBCTL, reg);
|
|
|
|
EPWM_WRITE2(sc, EPWM_TZCTL, 0xf);
|
|
reg = EPWM_READ2(sc, EPWM_TZFLG);
|
|
|
|
if ((sc->sc_busdev = device_add_child(dev, "pwmbus", -1)) == NULL) {
|
|
device_printf(dev, "Cannot add child pwmbus\n");
|
|
// This driver can still do things even without the bus child.
|
|
}
|
|
|
|
bus_generic_probe(dev);
|
|
return (bus_generic_attach(dev));
|
|
fail:
|
|
PWM_LOCK_DESTROY(sc);
|
|
if (sc->sc_mem_res)
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
sc->sc_mem_rid, sc->sc_mem_res);
|
|
|
|
return(ENXIO);
|
|
}
|
|
|
|
static int
|
|
am335x_ehrpwm_detach(device_t dev)
|
|
{
|
|
struct am335x_ehrpwm_softc *sc;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if ((error = bus_generic_detach(sc->sc_dev)) != 0)
|
|
return (error);
|
|
|
|
PWM_LOCK(sc);
|
|
|
|
if (sc->sc_busdev != NULL)
|
|
device_delete_child(dev, sc->sc_busdev);
|
|
|
|
if (sc->sc_mem_res)
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
sc->sc_mem_rid, sc->sc_mem_res);
|
|
|
|
PWM_UNLOCK(sc);
|
|
|
|
PWM_LOCK_DESTROY(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static phandle_t
|
|
am335x_ehrpwm_get_node(device_t bus, device_t dev)
|
|
{
|
|
|
|
/*
|
|
* Share our controller node with our pwmbus child; it instantiates
|
|
* devices by walking the children contained within our node.
|
|
*/
|
|
return ofw_bus_get_node(bus);
|
|
}
|
|
|
|
static device_method_t am335x_ehrpwm_methods[] = {
|
|
DEVMETHOD(device_probe, am335x_ehrpwm_probe),
|
|
DEVMETHOD(device_attach, am335x_ehrpwm_attach),
|
|
DEVMETHOD(device_detach, am335x_ehrpwm_detach),
|
|
|
|
/* ofw_bus_if */
|
|
DEVMETHOD(ofw_bus_get_node, am335x_ehrpwm_get_node),
|
|
|
|
/* pwm interface */
|
|
DEVMETHOD(pwmbus_channel_count, am335x_ehrpwm_channel_count),
|
|
DEVMETHOD(pwmbus_channel_config, am335x_ehrpwm_channel_config),
|
|
DEVMETHOD(pwmbus_channel_get_config, am335x_ehrpwm_channel_get_config),
|
|
DEVMETHOD(pwmbus_channel_enable, am335x_ehrpwm_channel_enable),
|
|
DEVMETHOD(pwmbus_channel_is_enabled, am335x_ehrpwm_channel_is_enabled),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t am335x_ehrpwm_driver = {
|
|
"pwm",
|
|
am335x_ehrpwm_methods,
|
|
sizeof(struct am335x_ehrpwm_softc),
|
|
};
|
|
|
|
static devclass_t am335x_ehrpwm_devclass;
|
|
|
|
DRIVER_MODULE(am335x_ehrpwm, am335x_pwmss, am335x_ehrpwm_driver, am335x_ehrpwm_devclass, 0, 0);
|
|
MODULE_VERSION(am335x_ehrpwm, 1);
|
|
MODULE_DEPEND(am335x_ehrpwm, am335x_pwmss, 1, 1, 1);
|
|
MODULE_DEPEND(am335x_ehrpwm, pwmbus, 1, 1, 1);
|