97 lines
3.2 KiB
C
97 lines
3.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
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*
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* Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _TI_DPLL_CLOCK_H_
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#define _TI_DPLL_CLOCK_H_
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#include <dev/extres/clk/clk.h>
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/* Registers are described in AM335x TRM chapter 8.1.12.2.* */
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/* Register offsets */
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#define CM_CLKSEL_DPLL_PERIPH 0x49C
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/* CM_IDLEST_DPLL_xxx */
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#define ST_MN_BYPASS_MASK 0x0100
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#define ST_MN_BYPASS_SHIFT 8
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#define ST_DPLL_CLK_MASK 0x0001
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/* CM_CLKMODE_DPLL_DPLL_EN feature flag */
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#define LOW_POWER_STOP_MODE_FLAG 0x01
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#define MN_BYPASS_MODE_FLAG 0x02
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#define IDLE_BYPASS_LOW_POWER_MODE_FLAG 0x04
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#define IDLE_BYPASS_FAST_RELOCK_MODE_FLAG 0x08
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#define LOCK_MODE_FLAG 0x10
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/* CM_CLKMODE_DPLL_xxx */
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#define DPLL_EN_LOW_POWER_STOP_MODE 0x01
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#define DPLL_EN_MN_BYPASS_MODE 0x04
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#define DPLL_EN_IDLE_BYPASS_LOW_POWER_MODE 0x05
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#define DPLL_EN_IDLE_BYPASS_FAST_RELOCK_MODE 0x06
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#define DPLL_EN_LOCK_MODE 0x07
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#define TI_CLK_FACTOR_ZERO_BASED 0x0002
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#define TI_CLK_FACTOR_FIXED 0x0008
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#define TI_CLK_FACTOR_MIN_VALUE 0x0020
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#define TI_CLK_FACTOR_MAX_VALUE 0x0040
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/* Based on aw_clk_factor sys/arm/allwinner/clkng/aw_clk.h */
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struct ti_clk_factor {
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uint32_t shift; /* Shift bits for the factor */
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uint32_t mask; /* Mask to get the factor */
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uint32_t width; /* Number of bits for the factor */
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uint32_t value; /* Fixed value */
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uint32_t min_value;
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uint32_t max_value;
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uint32_t flags; /* Flags */
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};
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struct ti_clk_dpll_def {
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struct clknode_init_def clkdef;
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uint32_t ti_clkmode_offset; /* control */
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uint8_t ti_clkmode_flags;
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uint32_t ti_idlest_offset;
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uint32_t ti_clksel_offset; /* mult-div1 */
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struct ti_clk_factor ti_clksel_mult;
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struct ti_clk_factor ti_clksel_div;
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uint32_t ti_autoidle_offset;
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};
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int ti_clknode_dpll_register(struct clkdom *clkdom, struct ti_clk_dpll_def *clkdef);
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#endif /* _TI_DPLL_CLOCK_H_ */
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