04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
300 lines
14 KiB
C
300 lines
14 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-mpi-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon mpi.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_MPI_TYPEDEFS_H__
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#define __CVMX_MPI_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
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static inline uint64_t CVMX_MPI_CFG_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
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cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070000001000ull);
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}
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#else
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#define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
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(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
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(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8)))))
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cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8;
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}
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#else
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#define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
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static inline uint64_t CVMX_MPI_STS_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
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cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070000001008ull);
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}
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#else
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#define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
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static inline uint64_t CVMX_MPI_TX_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
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cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070000001010ull);
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}
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#else
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#define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
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#endif
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/**
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* cvmx_mpi_cfg
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*/
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union cvmx_mpi_cfg
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{
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uint64_t u64;
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struct cvmx_mpi_cfg_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_29_63 : 35;
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uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
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CLKDIV = Feclk / (2 * Fsclk) */
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uint64_t reserved_12_15 : 4;
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uint64_t cslate : 1; /**< If 0, MPI_CS asserts 1/2 SCLK before transaction
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1, MPI_CS assert coincident with transaction
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NOTE: only used if CSENA == 1 */
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uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
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expected to be driving
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1, MPI_TX pin is tristated when not transmitting
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NOTE: only used when WIREOR==1 */
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uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
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commands. */
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uint64_t cshi : 1; /**< If 0, CS is low asserted
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1, CS is high asserted */
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uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
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1, CS is driven per MPI_TX intruction */
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uint64_t int_ena : 1; /**< If 0, polling is required
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1, MPI engine interrupts X end of transaction */
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uint64_t lsbfirst : 1; /**< If 0, shift MSB first
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1, shift LSB first */
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uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
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MPI_TX pin is always driven
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1, MPI_TX/RX is all from MPI_TX pin (MPI)
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MPI_TX pin is tristated when not transmitting
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NOTE: if WIREOR==1, MPI_RX pin is not used by the
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MPI engine */
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uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
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completion of MPI transaction
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1, clock never idles, requires CS deassertion
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assertion between commands */
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uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
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1, MPI_CLK idles low, 1st transition is lo->hi */
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uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
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1, MPI_CLK, MPI_CS, and MPI_TX are driven */
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#else
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uint64_t enable : 1;
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uint64_t idlelo : 1;
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uint64_t clk_cont : 1;
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uint64_t wireor : 1;
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uint64_t lsbfirst : 1;
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uint64_t int_ena : 1;
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uint64_t csena : 1;
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uint64_t cshi : 1;
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uint64_t idleclks : 2;
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uint64_t tritx : 1;
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uint64_t cslate : 1;
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uint64_t reserved_12_15 : 4;
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uint64_t clkdiv : 13;
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uint64_t reserved_29_63 : 35;
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#endif
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} s;
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struct cvmx_mpi_cfg_s cn30xx;
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struct cvmx_mpi_cfg_cn31xx
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_29_63 : 35;
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uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
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CLKDIV = Feclk / (2 * Fsclk) */
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uint64_t reserved_11_15 : 5;
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uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
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expected to be driving
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1, MPI_TX pin is tristated when not transmitting
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NOTE: only used when WIREOR==1 */
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uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
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commands. */
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uint64_t cshi : 1; /**< If 0, CS is low asserted
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1, CS is high asserted */
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uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
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1, CS is driven per MPI_TX intruction */
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uint64_t int_ena : 1; /**< If 0, polling is required
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1, MPI engine interrupts X end of transaction */
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uint64_t lsbfirst : 1; /**< If 0, shift MSB first
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1, shift LSB first */
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uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
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MPI_TX pin is always driven
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1, MPI_TX/RX is all from MPI_TX pin (MPI)
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MPI_TX pin is tristated when not transmitting
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NOTE: if WIREOR==1, MPI_RX pin is not used by the
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MPI engine */
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uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
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completion of MPI transaction
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1, clock never idles, requires CS deassertion
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assertion between commands */
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uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
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1, MPI_CLK idles low, 1st transition is lo->hi */
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uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
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1, MPI_CLK, MPI_CS, and MPI_TX are driven */
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#else
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uint64_t enable : 1;
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uint64_t idlelo : 1;
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uint64_t clk_cont : 1;
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uint64_t wireor : 1;
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uint64_t lsbfirst : 1;
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uint64_t int_ena : 1;
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uint64_t csena : 1;
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uint64_t cshi : 1;
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uint64_t idleclks : 2;
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uint64_t tritx : 1;
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uint64_t reserved_11_15 : 5;
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uint64_t clkdiv : 13;
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uint64_t reserved_29_63 : 35;
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#endif
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} cn31xx;
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struct cvmx_mpi_cfg_s cn50xx;
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};
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typedef union cvmx_mpi_cfg cvmx_mpi_cfg_t;
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/**
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* cvmx_mpi_dat#
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*/
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union cvmx_mpi_datx
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{
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uint64_t u64;
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struct cvmx_mpi_datx_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_8_63 : 56;
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uint64_t data : 8; /**< Data to transmit/received */
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#else
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uint64_t data : 8;
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uint64_t reserved_8_63 : 56;
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#endif
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} s;
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struct cvmx_mpi_datx_s cn30xx;
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struct cvmx_mpi_datx_s cn31xx;
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struct cvmx_mpi_datx_s cn50xx;
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};
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typedef union cvmx_mpi_datx cvmx_mpi_datx_t;
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/**
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* cvmx_mpi_sts
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*/
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union cvmx_mpi_sts
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{
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uint64_t u64;
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struct cvmx_mpi_sts_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_13_63 : 51;
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uint64_t rxnum : 5; /**< Number of bytes written for transaction */
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uint64_t reserved_1_7 : 7;
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uint64_t busy : 1; /**< If 0, no MPI transaction in progress
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1, MPI engine is processing a transaction */
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#else
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uint64_t busy : 1;
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uint64_t reserved_1_7 : 7;
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uint64_t rxnum : 5;
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uint64_t reserved_13_63 : 51;
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#endif
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} s;
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struct cvmx_mpi_sts_s cn30xx;
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struct cvmx_mpi_sts_s cn31xx;
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struct cvmx_mpi_sts_s cn50xx;
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};
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typedef union cvmx_mpi_sts cvmx_mpi_sts_t;
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/**
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* cvmx_mpi_tx
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*/
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union cvmx_mpi_tx
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{
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uint64_t u64;
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struct cvmx_mpi_tx_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_17_63 : 47;
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uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done
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1, leave CS asserted after transactrion is done */
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uint64_t reserved_13_15 : 3;
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uint64_t txnum : 5; /**< Number of bytes to transmit */
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uint64_t reserved_5_7 : 3;
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uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) */
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#else
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uint64_t totnum : 5;
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uint64_t reserved_5_7 : 3;
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uint64_t txnum : 5;
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uint64_t reserved_13_15 : 3;
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uint64_t leavecs : 1;
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uint64_t reserved_17_63 : 47;
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#endif
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} s;
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struct cvmx_mpi_tx_s cn30xx;
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struct cvmx_mpi_tx_s cn31xx;
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struct cvmx_mpi_tx_s cn50xx;
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};
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typedef union cvmx_mpi_tx cvmx_mpi_tx_t;
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#endif
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