04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
153 lines
4.5 KiB
C
153 lines
4.5 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to power-throttle control, measurement, and debugging
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* facilities.
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*
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* <hr>$Revision<hr>
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*
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*/
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#include "cvmx.h"
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#include "cvmx-asm.h"
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#include "cvmx-power-throttle.h"
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#define CVMX_PTH_PPID_BCAST 63
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#define CVMX_PTH_PPID_MAX 64
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/**
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* @INTERNAL
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* Set the POWLIM field as percentage% of the MAXPOW field in r.
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*/
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static uint64_t __cvmx_power_throttle_set_powlim(uint64_t r, uint8_t percentage)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
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{
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uint64_t t;
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assert(percentage < 101);
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t = percentage * cvmx_power_throttle_get_field(CVMX_PTH_INDEX_MAXPOW, r) / 100;
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r = cvmx_power_throttle_set_field(CVMX_PTH_INDEX_POWLIM, r, t);
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return r;
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}
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return 0;
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}
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/**
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* @INTERNAL
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* Given ppid, calculate its PowThrottle register's L2C_COP0_MAP CSR
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* address. (ppid == PTH_PPID_BCAST is for broadcasting)
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*/
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static uint64_t __cvmx_power_throttle_csr_addr(uint64_t ppid)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
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{
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uint64_t csr_addr, reg_num, reg_reg, reg_sel;
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assert(ppid < CVMX_PTH_PPID_MAX);
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/*
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* register 11 selection 6
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*/
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reg_reg = 11;
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reg_sel = 6;
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reg_num = (ppid << 8) + (reg_reg << 3) + reg_sel;
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csr_addr = CVMX_L2C_COP0_MAPX(0) + ((reg_num) << 3);
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return csr_addr;
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}
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return 0;
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}
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/**
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* Throttle power to percentage% of configured maximum (MAXPOW).
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*
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* @param percentage 0 to 100
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* @return 0 for success
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*/
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int cvmx_power_throttle_self(uint8_t percentage)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
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{
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uint64_t r;
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CVMX_MF_COP0(r, COP0_POWTHROTTLE);
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r = __cvmx_power_throttle_set_powlim(r, percentage);
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CVMX_MT_COP0(r, COP0_POWTHROTTLE);
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}
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return 0;
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}
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/**
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* Throttle power to percentage% of configured maximum (MAXPOW)
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* for the cores identified in coremask.
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*
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* @param percentage 0 to 100
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* @param coremask bit mask where each bit identifies a core.
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* @return 0 for success.
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*/
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int cvmx_power_throttle(uint8_t percentage, uint64_t coremask)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
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{
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uint64_t ppid, csr_addr, b, r;
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b = 1;
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/*
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* cvmx_read_csr() for PTH_PPID_BCAST does not make sense and
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* therefore limit ppid to less.
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*/
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for (ppid = 0; ppid < CVMX_PTH_PPID_BCAST; ppid ++)
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{
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if ((b << ppid) & coremask) {
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csr_addr = __cvmx_power_throttle_csr_addr(ppid);
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r = cvmx_read_csr(csr_addr);
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r = __cvmx_power_throttle_set_powlim(r, percentage);
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cvmx_write_csr(csr_addr, r);
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}
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}
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}
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return 0;
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}
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