1fdcc5e5c0
RISC-V is a new ISA designed to support computer research and education, and is now become a standard open architecture for industry implementations. This is a minimal set of changes required to run 'make kernel-toolchain' using external (GNU) toolchain. The FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv. Reviewed by: andrew, bdrewery, emaste, imp Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4445
17 lines
532 B
Makefile
17 lines
532 B
Makefile
# $FreeBSD$
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.if ${MACHINE_ARCH} == "aarch64" || \
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${MACHINE_ARCH} == "amd64" || \
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${MACHINE_ARCH} == "i386" || \
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(${MACHINE} == "arm" && ${MACHINE_ARCH:Marm*eb*} == "") || \
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${MACHINE_CPUARCH} == "riscv" || \
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${MACHINE_ARCH:Mmips*el} != ""
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TARGET_ENDIANNESS= 1234
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.elif ${MACHINE_ARCH} == "powerpc" || \
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${MACHINE_ARCH} == "powerpc64" || \
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${MACHINE_ARCH} == "sparc64" || \
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(${MACHINE} == "arm" && ${MACHINE_ARCH:Marm*eb*} != "") || \
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${MACHINE_ARCH:Mmips*} != ""
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TARGET_ENDIANNESS= 4321
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.endif
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