d/freebsd-dev
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
20c776a50b
freebsd-dev/sys/i386/isa/clock.c
Peter Wemm 5400ed3b2f Include file updates.. <machine/spl.h> -> <machine/ipl.h>, add 
<machine/ipl.h> to those files that were depending on getting SWI_*
implicitly via <machine/cpufunc.h>
1997-05-31 09:27:31 +00:00

1036 lines
26 KiB
C
Raw Blame History

/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz and Don Ahn.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
* $Id: clock.c,v 1.85 1997/05/29 05:00:35 peter Exp $
*/
/*
* Routines to handle clock hardware.
*/
/*
* inittodr, settodr and support routines written
* by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
*
* reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
*/
#include "opt_clock.h"
#include "opt_cpu.h"
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/time.h>
#include <sys/kernel.h>
#include <sys/sysctl.h>
#include <machine/clock.h>
#ifdef CLK_CALIBRATION_LOOP
#include <machine/cons.h>
#endif
#include <machine/cpu.h>
#include <machine/frame.h>
#include <machine/ipl.h>
#include <i386/isa/icu.h>
#include <i386/isa/isa.h>
#include <i386/isa/isa_device.h>
#include <i386/isa/rtc.h>
#include <i386/isa/timerreg.h>
/*
* 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
* can use a simple formula for leap years.
*/
#define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
/*
* Time in timer cycles that it takes for microtime() to disable interrupts
* and latch the count. microtime() currently uses "cli; outb ..." so it
* normally takes less than 2 timer cycles. Add a few for cache misses.
* Add a few more to allow for latency in bogus calls to microtime() with
* interrupts already disabled.
*/
#define TIMER0_LATCH_COUNT 20
/*
* Maximum frequency that we are willing to allow for timer0. Must be
* low enough to guarantee that the timer interrupt handler returns
* before the next timer interrupt. Must result in a lower TIMER_DIV
* value than TIMER0_LATCH_COUNT so that we don't have to worry about
* underflow in the calculation of timer0_overflow_threshold.
*/
#define TIMER0_MAX_FREQ 20000
int adjkerntz; /* local offset from GMT in seconds */
int disable_rtc_set; /* disable resettodr() if != 0 */
u_int idelayed;
#if defined(I586_CPU) || defined(I686_CPU)
#ifndef SMP
u_int i586_ctr_bias;
u_int i586_ctr_comultiplier;
#endif
u_int i586_ctr_freq;
#ifndef SMP
u_int i586_ctr_multiplier;
#endif
#endif
int statclock_disable;
u_int stat_imask = SWI_CLOCK_MASK;
#ifdef TIMER_FREQ
u_int timer_freq = TIMER_FREQ;
#else
u_int timer_freq = 1193182;
#endif
int timer0_max_count;
u_int timer0_overflow_threshold;
u_int timer0_prescaler_count;
int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
static int beeping = 0;
static u_int clk_imask = HWI_MASK | SWI_MASK;
static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
static u_int hardclock_max_count;
/*
* XXX new_function and timer_func should not handle clockframes, but
* timer_func currently needs to hold hardclock to handle the
* timer0_state == 0 case. We should use register_intr()/unregister_intr()
* to switch between clkintr() and a slightly different timerintr().
*/
static void (*new_function) __P((struct clockframe *frame));
static u_int new_rate;
static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
/* Values for timerX_state: */
#define RELEASED 0
#define RELEASE_PENDING 1
#define ACQUIRED 2
#define ACQUIRE_PENDING 3
static u_char timer0_state;
static u_char timer2_state;
static void (*timer_func) __P((struct clockframe *frame)) = hardclock;
#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq);
#endif
static void set_timer_freq(u_int freq, int intr_freq);
static void
clkintr(struct clockframe frame)
{
timer_func(&frame);
switch (timer0_state) {
case RELEASED:
setdelayed();
break;
case ACQUIRED:
if ((timer0_prescaler_count += timer0_max_count)
>= hardclock_max_count) {
hardclock(&frame);
setdelayed();
timer0_prescaler_count -= hardclock_max_count;
}
break;
case ACQUIRE_PENDING:
setdelayed();
timer0_max_count = TIMER_DIV(new_rate);
timer0_overflow_threshold =
timer0_max_count - TIMER0_LATCH_COUNT;
disable_intr();
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
outb(TIMER_CNTR0, timer0_max_count & 0xff);
outb(TIMER_CNTR0, timer0_max_count >> 8);
enable_intr();
timer0_prescaler_count = 0;
timer_func = new_function;
timer0_state = ACQUIRED;
break;
case RELEASE_PENDING:
if ((timer0_prescaler_count += timer0_max_count)
>= hardclock_max_count) {
hardclock(&frame);
setdelayed();
timer0_max_count = hardclock_max_count;
timer0_overflow_threshold =
timer0_max_count - TIMER0_LATCH_COUNT;
disable_intr();
outb(TIMER_MODE,
TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
outb(TIMER_CNTR0, timer0_max_count & 0xff);
outb(TIMER_CNTR0, timer0_max_count >> 8);
enable_intr();
/*
* See microtime.s for this magic.
*/
time.tv_usec += (27465 *
(timer0_prescaler_count - hardclock_max_count))
>> 15;
if (time.tv_usec >= 1000000)
time.tv_usec -= 1000000;
timer0_prescaler_count = 0;
timer_func = hardclock;
timer0_state = RELEASED;
}
break;
}
}
/*
* The acquire and release functions must be called at ipl >= splclock().
*/
int
acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
{
static int old_rate;
if (rate <= 0 || rate > TIMER0_MAX_FREQ)
return (-1);
switch (timer0_state) {
case RELEASED:
timer0_state = ACQUIRE_PENDING;
break;
case RELEASE_PENDING:
if (rate != old_rate)
return (-1);
/*
* The timer has been released recently, but is being
* re-acquired before the release completed. In this
* case, we simply reclaim it as if it had not been
* released at all.
*/
timer0_state = ACQUIRED;
break;
default:
return (-1); /* busy */
}
new_function = function;
old_rate = new_rate = rate;
return (0);
}
int
acquire_timer2(int mode)
{
if (timer2_state != RELEASED)
return (-1);
timer2_state = ACQUIRED;
/*
* This access to the timer registers is as atomic as possible
* because it is a single instruction. We could do better if we
* knew the rate. Use of splclock() limits glitches to 10-100us,
* and this is probably good enough for timer2, so we aren't as
* careful with it as with timer0.
*/
outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
return (0);
}
int
release_timer0()
{
switch (timer0_state) {
case ACQUIRED:
timer0_state = RELEASE_PENDING;
break;
case ACQUIRE_PENDING:
/* Nothing happened yet, release quickly. */
timer0_state = RELEASED;
break;
default:
return (-1);
}
return (0);
}
int
release_timer2()
{
if (timer2_state != ACQUIRED)
return (-1);
timer2_state = RELEASED;
outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
return (0);
}
/*
* This routine receives statistical clock interrupts from the RTC.
* As explained above, these occur at 128 interrupts per second.
* When profiling, we receive interrupts at a rate of 1024 Hz.
*
* This does not actually add as much overhead as it sounds, because
* when the statistical clock is active, the hardclock driver no longer
* needs to keep (inaccurate) statistics on its own. This decouples
* statistics gathering from scheduling interrupts.
*
* The RTC chip requires that we read status register C (RTC_INTR)
* to acknowledge an interrupt, before it will generate the next one.
* Under high interrupt load, rtcintr() can be indefinitely delayed and
* the clock can tick immediately after the read from RTC_INTR. In this
* case, the mc146818A interrupt signal will not drop for long enough
* to register with the 8259 PIC. If an interrupt is missed, the stat
* clock will halt, considerably degrading system performance. This is
* why we use 'while' rather than a more straightforward 'if' below.
* Stat clock ticks can still be lost, causing minor loss of accuracy
* in the statistics, but the stat clock will no longer stop.
*/
static void
rtcintr(struct clockframe frame)
{
while (rtcin(RTC_INTR) & RTCIR_PERIOD)
statclock(&frame);
}
#include "opt_ddb.h"
#ifdef DDB
#include <ddb/ddb.h>
DB_SHOW_COMMAND(rtc, rtc)
{
printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
}
#endif /* DDB */
static int
getit(void)
{
u_long ef;
int high, low;
ef = read_eflags();
disable_intr();
/* Select timer0 and latch counter value. */
outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
low = inb(TIMER_CNTR0);
high = inb(TIMER_CNTR0);
write_eflags(ef);
return ((high << 8) | low);
}
/*
* Wait "n" microseconds.
* Relies on timer 1 counting down from (timer_freq / hz)
* Note: timer had better have been programmed before this is first used!
*/
void
DELAY(int n)
{
int delta, prev_tick, tick, ticks_left;
#ifdef DELAYDEBUG
int getit_calls = 1;
int n1;
static int state = 0;
if (state == 0) {
state = 1;
for (n1 = 1; n1 <= 10000000; n1 *= 10)
DELAY(n1);
state = 2;
}
if (state == 1)
printf("DELAY(%d)...", n);
#endif
/*
* Guard against the timer being uninitialized if we are called
* early for console i/o.
*/
if (timer0_max_count == 0)
set_timer_freq(timer_freq, hz);
/*
* Read the counter first, so that the rest of the setup overhead is
* counted. Guess the initial overhead is 20 usec (on most systems it
* takes about 1.5 usec for each of the i/o's in getit(). The loop
* takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
* multiplications and divisions to scale the count take a while).
*/
prev_tick = getit();
n -= 0; /* XXX actually guess no initial overhead */
/*
* Calculate (n * (timer_freq / 1e6)) without using floating point
* and without any avoidable overflows.
*/
if (n <= 0)
ticks_left = 0;
else if (n < 256)
/*
* Use fixed point to avoid a slow division by 1000000.
* 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
* 2^15 is the first power of 2 that gives exact results
* for n between 0 and 256.
*/
ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
else
/*
* Don't bother using fixed point, although gcc-2.7.2
* generates particularly poor code for the long long
* division, since even the slow way will complete long
* before the delay is up (unless we're interrupted).
*/
ticks_left = ((u_int)n * (long long)timer_freq + 999999)
/ 1000000;
while (ticks_left > 0) {
tick = getit();
#ifdef DELAYDEBUG
++getit_calls;
#endif
delta = prev_tick - tick;
prev_tick = tick;
if (delta < 0) {
delta += timer0_max_count;
/*
* Guard against timer0_max_count being wrong.
* This shouldn't happen in normal operation,
* but it may happen if set_timer_freq() is
* traced.
*/
if (delta < 0)
delta = 0;
}
ticks_left -= delta;
}
#ifdef DELAYDEBUG
if (state == 1)
printf(" %d calls to getit() at %d usec each\n",
getit_calls, (n + 5) / getit_calls);
#endif
}
static void
sysbeepstop(void *chan)
{
outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
release_timer2();
beeping = 0;
}
int
sysbeep(int pitch, int period)
{
int x = splclock();
if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
if (!beeping) {
/* Something else owns it. */
splx(x);
return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
}
disable_intr();
outb(TIMER_CNTR2, pitch);
outb(TIMER_CNTR2, (pitch>>8));
enable_intr();
if (!beeping) {
/* enable counter2 output to speaker */
outb(IO_PPI, inb(IO_PPI) | 3);
beeping = period;
timeout(sysbeepstop, (void *)NULL, period);
}
splx(x);
return (0);
}
/*
* RTC support routines
*/
int
rtcin(reg)
int reg;
{
u_char val;
outb(IO_RTC, reg);
inb(0x84);
val = inb(IO_RTC + 1);
inb(0x84);
return (val);
}
static __inline void
writertc(u_char reg, u_char val)
{
outb(IO_RTC, reg);
outb(IO_RTC + 1, val);
}
static __inline int
readrtc(int port)
{
return(bcd2bin(rtcin(port)));
}
static u_int
calibrate_clocks(void)
{
u_int count, prev_count, tot_count;
int sec, start_sec, timeout;
if (bootverbose)
printf("Calibrating clock(s) ... ");
if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
goto fail;
timeout = 100000000;
/* Read the mc146818A seconds counter. */
for (;;) {
if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
sec = rtcin(RTC_SEC);
break;
}
if (--timeout == 0)
goto fail;
}
/* Wait for the mC146818A seconds counter to change. */
start_sec = sec;
for (;;) {
if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
sec = rtcin(RTC_SEC);
if (sec != start_sec)
break;
}
if (--timeout == 0)
goto fail;
}
/* Start keeping track of the i8254 counter. */
prev_count = getit();
if (prev_count == 0 || prev_count > timer0_max_count)
goto fail;
tot_count = 0;
#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)
wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */
#endif
/*
* Wait for the mc146818A seconds counter to change. Read the i8254
* counter for each iteration since this is convenient and only
* costs a few usec of inaccuracy. The timing of the final reads
* of the counters almost matches the timing of the initial reads,
* so the main cause of inaccuracy is the varying latency from
* inside getit() or rtcin(RTC_STATUSA) to the beginning of the
* rtcin(RTC_SEC) that returns a changed seconds count. The
* maximum inaccuracy from this cause is < 10 usec on 486's.
*/
start_sec = sec;
for (;;) {
if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
sec = rtcin(RTC_SEC);
count = getit();
if (count == 0 || count > timer0_max_count)
goto fail;
if (count > prev_count)
tot_count += prev_count - (count - timer0_max_count);
else
tot_count += prev_count - count;
prev_count = count;
if (sec != start_sec)
break;
if (--timeout == 0)
goto fail;
}
#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
/*
* Read the cpu cycle counter. The timing considerations are
* similar to those for the i8254 clock.
*/
if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) {
set_i586_ctr_freq((u_int)rdtsc(), tot_count);
if (bootverbose)
printf("i586 clock: %u Hz, ", i586_ctr_freq);
}
#endif
if (bootverbose)
printf("i8254 clock: %u Hz\n", tot_count);
return (tot_count);
fail:
if (bootverbose)
printf("failed, using default i8254 clock of %u Hz\n",
timer_freq);
return (timer_freq);
}
static void
set_timer_freq(u_int freq, int intr_freq)
{
u_long ef;
ef = read_eflags();
disable_intr();
timer_freq = freq;
timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT;
outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
outb(TIMER_CNTR0, timer0_max_count & 0xff);
outb(TIMER_CNTR0, timer0_max_count >> 8);
write_eflags(ef);
}
/*
* Initialize 8253 timer 0 early so that it can be used in DELAY().
* XXX initialization of other timers is unintentionally left blank.
*/
void
startrtclock()
{
u_int delta, freq;
writertc(RTC_STATUSA, rtc_statusa);
writertc(RTC_STATUSB, RTCSB_24HR);
set_timer_freq(timer_freq, hz);
freq = calibrate_clocks();
#ifdef CLK_CALIBRATION_LOOP
if (bootverbose) {
printf(
"Press a key on the console to abort clock calibration\n");
while (cncheckc() == -1)
calibrate_clocks();
}
#endif
/*
* Use the calibrated i8254 frequency if it seems reasonable.
* Otherwise use the default, and don't use the calibrated i586
* frequency.
*/
delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
if (delta < timer_freq / 100) {
#ifndef CLK_USE_I8254_CALIBRATION
if (bootverbose)
printf(
"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
freq = timer_freq;
#endif
timer_freq = freq;
} else {
if (bootverbose)
printf(
"%d Hz differs from default of %d Hz by more than 1%%\n",
freq, timer_freq);
#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
i586_ctr_freq = 0;
#endif
}
set_timer_freq(timer_freq, hz);
#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
#ifndef CLK_USE_I586_CALIBRATION
if (i586_ctr_freq != 0) {
if (bootverbose)
printf(
"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n");
i586_ctr_freq = 0;
}
#endif
if (i586_ctr_freq == 0 &&
(cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) {
/*
* Calibration of the i586 clock relative to the mc146818A
* clock failed. Do a less accurate calibration relative
* to the i8254 clock.
*/
wrmsr(0x10, 0LL); /* XXX */
DELAY(1000000);
set_i586_ctr_freq((u_int)rdtsc(), timer_freq);
#ifdef CLK_USE_I586_CALIBRATION
if (bootverbose)
printf("i586 clock: %u Hz\n", i586_ctr_freq);
#endif
}
#endif
}
/*
* Initialize the time of day register, based on the time base which is, e.g.
* from a filesystem.
*/
void
inittodr(time_t base)
{
unsigned long sec, days;
int yd;
int year, month;
int y, m, s;
s = splclock();
time.tv_sec = base;
time.tv_usec = 0;
splx(s);
/* Look if we have a RTC present and the time is valid */
if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
goto wrong_time;
/* wait for time update to complete */
/* If RTCSA_TUP is zero, we have at least 244us before next update */
while (rtcin(RTC_STATUSA) & RTCSA_TUP);
days = 0;
#ifdef USE_RTC_CENTURY
year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
#else
year = readrtc(RTC_YEAR) + 1900;
if (year < 1970)
year += 100;
#endif
if (year < 1970)
goto wrong_time;
month = readrtc(RTC_MONTH);
for (m = 1; m < month; m++)
days += daysinmonth[m-1];
if ((month > 2) && LEAPYEAR(year))
days ++;
days += readrtc(RTC_DAY) - 1;
yd = days;
for (y = 1970; y < year; y++)
days += DAYSPERYEAR + LEAPYEAR(y);
sec = ((( days * 24 +
readrtc(RTC_HRS)) * 60 +
readrtc(RTC_MIN)) * 60 +
readrtc(RTC_SEC));
/* sec now contains the number of seconds, since Jan 1 1970,
in the local time zone */
sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
s = splclock();
time.tv_sec = sec;
splx(s);
return;
wrong_time:
printf("Invalid time in real time clock.\n");
printf("Check and reset the date immediately!\n");
}
/*
* Write system time back to RTC
*/
void
resettodr()
{
unsigned long tm;
int y, m, s;
if (disable_rtc_set)
return;
s = splclock();
tm = time.tv_sec;
splx(s);
/* Disable RTC updates and interrupts. */
writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
/* Calculate local time to put in RTC */
tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
/* We have now the days since 01-01-1970 in tm */
writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
tm >= m;
y++, m = DAYSPERYEAR + LEAPYEAR(y))
tm -= m;
/* Now we have the years in y and the day-of-the-year in tm */
writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
#ifdef USE_RTC_CENTURY
writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
#endif
for (m = 0; ; m++) {
int ml;
ml = daysinmonth[m];
if (m == 1 && LEAPYEAR(y))
ml++;
if (tm < ml)
break;
tm -= ml;
}
writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
/* Reenable RTC updates and interrupts. */
writertc(RTC_STATUSB, rtc_statusb);
}
#if defined(APIC_IO)
/* from icu.s: */
extern u_int vec[];
extern void vec8254 __P((void));
extern void vecRTC __P((void));
extern u_int ivectors[];
extern u_int Xintr8254;
extern u_int XintrRTC;
extern u_int mask8254;
extern u_int maskRTC;
#endif /* APIC_IO */
/*
* Start both clocks running.
*/
void
cpu_initclocks()
{
int diag;
#if defined(APIC_IO)
int x;
#endif /* APIC_IO */
if (statclock_disable) {
/*
* The stat interrupt mask is different without the
* statistics clock. Also, don't set the interrupt
* flag which would normally cause the RTC to generate
* interrupts.
*/
stat_imask = HWI_MASK | SWI_MASK;
rtc_statusb = RTCSB_24HR;
} else {
/* Setting stathz to nonzero early helps avoid races. */
stathz = RTC_NOPROFRATE;
profhz = RTC_PROFRATE;
}
/* Finish initializing 8253 timer 0. */
#if defined(APIC_IO)
/* 8254 is traditionally on ISA IRQ0 */
if ((x = get_isa_apic_irq(0)) < 0) {
/*
* bummer, this mb doesn't have the 8254 on ISA irq0,
* perhaps it's on the EISA bus...
*/
if ((x = get_eisa_apic_irq(0)) < 0) {
/* double bummer, attempt to redirect thru the 8259 */
if (bootverbose)
printf("APIC missing 8254 connection\n");
/* allow 8254 timer to INTerrupt 8259 */
#if !defined(IO_ICU1)
#define IO_ICU1 0x20
#endif
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
/* program IO APIC for type 3 INT on INT0 */
if (ext_int_setup(0, 0) < 0)
panic("8254 redirect impossible!");
x = 0; /* 8259 is on 0 */
}
}
vec[x] = (u_int)vec8254;
Xintr8254 = (u_int)ivectors[x]; /* XXX might need Xfastintr# */
mask8254 = (1 << x);
register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0,
/* XXX */ (inthand2_t *)clkintr, &clk_imask,
/* unit */ 0);
INTREN(mask8254);
#else
register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
/* XXX */ (inthand2_t *)clkintr, &clk_imask,
/* unit */ 0);
INTREN(IRQ0);
#endif /* APIC_IO */
#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
/*
* Finish setting up anti-jitter measures.
*/
if (i586_ctr_freq != 0)
i586_ctr_bias = rdtsc();
#endif
/* Initialize RTC. */
writertc(RTC_STATUSA, rtc_statusa);
writertc(RTC_STATUSB, RTCSB_24HR);
/* Don't bother enabling the statistics clock. */
if (statclock_disable)
return;
diag = rtcin(RTC_DIAG);
if (diag != 0)
printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
#if defined(APIC_IO)
/* RTC is traditionally on ISA IRQ8 */
if ((x = get_isa_apic_irq(8)) < 0) {
if ((x = get_eisa_apic_irq(8)) < 0) {
panic("APIC missing RTC connection");
}
}
vec[x] = (u_int)vecRTC;
XintrRTC = (u_int)ivectors[x]; /* XXX might need Xfastintr# */
maskRTC = (1 << x);
register_intr(/* irq */ x, /* XXX id */ 1, /* flags */ 0,
/* XXX */ (inthand2_t *)rtcintr, &stat_imask,
/* unit */ 0);
INTREN(maskRTC);
#else
register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0,
/* XXX */ (inthand2_t *)rtcintr, &stat_imask,
/* unit */ 0);
INTREN(IRQ8);
#endif /* APIC_IO */
writertc(RTC_STATUSB, rtc_statusb);
#if defined(APIC_IO)
printf("Enabled INTs: ");
for (x = 0; x < 24; ++x)
if ((imen & (1 << x)) == 0)
printf("%d, ", x);
printf("imen: 0x%08x\n", imen);
#endif /* APIC_IO */
}
void
setstatclockrate(int newhz)
{
if (newhz == RTC_PROFRATE)
rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
else
rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
writertc(RTC_STATUSA, rtc_statusa);
}
static int
sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS
{
int error;
u_int freq;
/*
* Use `i8254' instead of `timer' in external names because `timer'
* is is too generic. Should use it everywhere.
*/
freq = timer_freq;
error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req);
if (error == 0 && req->newptr != NULL) {
if (timer0_state != 0)
return (EBUSY); /* too much trouble to handle */
set_timer_freq(freq, hz);
#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
set_i586_ctr_freq(i586_ctr_freq, timer_freq);
#endif
}
return (error);
}
SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", "");
#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP)
static void
set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq)
{
u_int comultiplier, multiplier;
u_long ef;
if (i586_freq == 0) {
i586_ctr_freq = i586_freq;
return;
}
comultiplier = ((unsigned long long)i586_freq
<< I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq;
multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq;
ef = read_eflags();
disable_intr();
i586_ctr_freq = i586_freq;
i586_ctr_comultiplier = comultiplier;
i586_ctr_multiplier = multiplier;
write_eflags(ef);
}
static int
sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS
{
int error;
u_int freq;
if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686)
return (EOPNOTSUPP);
freq = i586_ctr_freq;
error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req);
if (error == 0 && req->newptr != NULL)
set_i586_ctr_freq(freq, timer_freq);
return (error);
}
SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW,
0, sizeof(u_int), sysctl_machdep_i586_freq, "I", "");
#endif /* (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) */
Reference in New Issue View Git Blame Copy Permalink