752ba93078
that provides the inverse translation, OF_xref_from_node(). Discussed with: nwhitehorn
663 lines
14 KiB
C
663 lines
14 KiB
C
/*-
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* Copyright (c) 2006 Benno Rice.
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* Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Adapted and extended for Marvell SoCs by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/interrupt.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/queue.h>
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#include <sys/timetc.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/mv/mvvar.h>
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#include <arm/mv/mvreg.h>
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#define GPIO_MAX_INTR_COUNT 8
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#define GPIO_PINS_PER_REG 32
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struct mv_gpio_softc {
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struct resource * res[GPIO_MAX_INTR_COUNT + 1];
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void *ih_cookie[GPIO_MAX_INTR_COUNT];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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uint8_t pin_num; /* number of GPIO pins */
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uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
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};
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extern struct resource_spec mv_gpio_res[];
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static struct mv_gpio_softc *mv_gpio_softc = NULL;
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static uint32_t gpio_setup[MV_GPIO_MAX_NPINS];
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static int mv_gpio_probe(device_t);
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static int mv_gpio_attach(device_t);
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static int mv_gpio_intr(void *);
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static int mv_gpio_init(void);
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static void mv_gpio_intr_handler(int pin);
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static uint32_t mv_gpio_reg_read(uint32_t reg);
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static void mv_gpio_reg_write(uint32_t reg, uint32_t val);
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static void mv_gpio_reg_set(uint32_t reg, uint32_t val);
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static void mv_gpio_reg_clear(uint32_t reg, uint32_t val);
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static void mv_gpio_blink(uint32_t pin, uint8_t enable);
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static void mv_gpio_polarity(uint32_t pin, uint8_t enable);
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static void mv_gpio_level(uint32_t pin, uint8_t enable);
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static void mv_gpio_edge(uint32_t pin, uint8_t enable);
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static void mv_gpio_out_en(uint32_t pin, uint8_t enable);
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static void mv_gpio_int_ack(uint32_t pin);
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static void mv_gpio_value_set(uint32_t pin, uint8_t val);
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static uint32_t mv_gpio_value_get(uint32_t pin);
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static device_method_t mv_gpio_methods[] = {
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DEVMETHOD(device_probe, mv_gpio_probe),
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DEVMETHOD(device_attach, mv_gpio_attach),
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{ 0, 0 }
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};
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static driver_t mv_gpio_driver = {
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"gpio",
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mv_gpio_methods,
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sizeof(struct mv_gpio_softc),
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};
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static devclass_t mv_gpio_devclass;
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DRIVER_MODULE(gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0);
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typedef int (*gpios_phandler_t)(phandle_t, pcell_t *, int);
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struct gpio_ctrl_entry {
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const char *compat;
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gpios_phandler_t handler;
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};
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int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len);
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int gpio_get_config_from_dt(void);
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struct gpio_ctrl_entry gpio_controllers[] = {
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{ "mrvl,gpio", &mv_handle_gpios_prop },
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{ NULL, NULL }
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};
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static int
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mv_gpio_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "mrvl,gpio"))
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return (ENXIO);
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device_set_desc(dev, "Marvell Integrated GPIO Controller");
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return (0);
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}
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static int
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mv_gpio_attach(device_t dev)
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{
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int error, i;
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struct mv_gpio_softc *sc;
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uint32_t dev_id, rev_id;
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sc = (struct mv_gpio_softc *)device_get_softc(dev);
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if (sc == NULL)
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return (ENXIO);
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mv_gpio_softc = sc;
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/* Get chip id and revision */
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soc_id(&dev_id, &rev_id);
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if (dev_id == MV_DEV_88F5182 ||
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dev_id == MV_DEV_88F5281 ||
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dev_id == MV_DEV_MV78100 ||
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dev_id == MV_DEV_MV78100_Z0 ) {
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sc->pin_num = 32;
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sc->irq_num = 4;
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} else if (dev_id == MV_DEV_88F6281 ||
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dev_id == MV_DEV_88F6282) {
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sc->pin_num = 50;
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sc->irq_num = 7;
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} else {
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device_printf(dev, "unknown chip id=0x%x\n", dev_id);
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return (ENXIO);
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}
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error = bus_alloc_resources(dev, mv_gpio_res, sc->res);
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if (error) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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/* Disable and clear all interrupts */
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bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0);
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bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0);
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bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0);
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if (sc->pin_num > GPIO_PINS_PER_REG) {
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bus_space_write_4(sc->bst, sc->bsh,
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GPIO_HI_INT_EDGE_MASK, 0);
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bus_space_write_4(sc->bst, sc->bsh,
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GPIO_HI_INT_LEV_MASK, 0);
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bus_space_write_4(sc->bst, sc->bsh,
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GPIO_HI_INT_CAUSE, 0);
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}
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for (i = 0; i < sc->irq_num; i++) {
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if (bus_setup_intr(dev, sc->res[1 + i],
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INTR_TYPE_MISC, mv_gpio_intr, NULL,
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sc, &sc->ih_cookie[i]) != 0) {
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bus_release_resources(dev, mv_gpio_res, sc->res);
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device_printf(dev, "could not set up intr %d\n", i);
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return (ENXIO);
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}
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}
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return (mv_gpio_init());
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}
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static int
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mv_gpio_intr(void *arg)
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{
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uint32_t int_cause, gpio_val;
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uint32_t int_cause_hi, gpio_val_hi = 0;
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int i;
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int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE);
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gpio_val = mv_gpio_reg_read(GPIO_DATA_IN);
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gpio_val &= int_cause;
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if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
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int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE);
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gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN);
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gpio_val_hi &= int_cause_hi;
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}
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i = 0;
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while (gpio_val != 0) {
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if (gpio_val & 1)
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mv_gpio_intr_handler(i);
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gpio_val >>= 1;
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i++;
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}
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if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
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i = 0;
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while (gpio_val_hi != 0) {
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if (gpio_val_hi & 1)
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mv_gpio_intr_handler(i + GPIO_PINS_PER_REG);
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gpio_val_hi >>= 1;
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i++;
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}
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}
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return (FILTER_HANDLED);
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}
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/*
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* GPIO interrupt handling
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*/
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static struct intr_event *gpio_events[MV_GPIO_MAX_NPINS];
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int
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mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
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void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
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{
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struct intr_event *event;
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int error;
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if (pin < 0 || pin >= mv_gpio_softc->pin_num)
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return (ENXIO);
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event = gpio_events[pin];
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if (event == NULL) {
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error = intr_event_create(&event, (void *)pin, 0, pin,
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(void (*)(void *))mv_gpio_intr_mask,
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(void (*)(void *))mv_gpio_intr_unmask,
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(void (*)(void *))mv_gpio_int_ack,
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NULL,
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"gpio%d:", pin);
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if (error != 0)
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return (error);
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gpio_events[pin] = event;
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}
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intr_event_add_handler(event, name, filt, hand, arg,
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intr_priority(flags), flags, cookiep);
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return (0);
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}
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void
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mv_gpio_intr_mask(int pin)
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{
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if (pin >= mv_gpio_softc->pin_num)
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return;
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if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
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mv_gpio_edge(pin, 0);
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else
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mv_gpio_level(pin, 0);
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}
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void
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mv_gpio_intr_unmask(int pin)
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{
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if (pin >= mv_gpio_softc->pin_num)
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return;
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if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
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mv_gpio_edge(pin, 1);
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else
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mv_gpio_level(pin, 1);
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}
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static void
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mv_gpio_intr_handler(int pin)
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{
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struct intr_event *event;
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event = gpio_events[pin];
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if (event == NULL || TAILQ_EMPTY(&event->ie_handlers))
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return;
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intr_event_handle(event, NULL);
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}
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static int
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mv_gpio_configure(uint32_t pin, uint32_t flags)
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{
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if (pin >= mv_gpio_softc->pin_num)
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return (EINVAL);
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if (flags & MV_GPIO_OUT_BLINK)
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mv_gpio_blink(pin, 1);
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if (flags & MV_GPIO_IN_POL_LOW)
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mv_gpio_polarity(pin, 1);
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if (flags & MV_GPIO_IN_IRQ_EDGE)
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mv_gpio_edge(pin, 1);
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if (flags & MV_GPIO_IN_IRQ_LEVEL)
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mv_gpio_level(pin, 1);
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gpio_setup[pin] = flags;
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return (0);
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}
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void
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mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable)
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{
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mv_gpio_value_set(pin, val);
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mv_gpio_out_en(pin, enable);
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}
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uint8_t
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mv_gpio_in(uint32_t pin)
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{
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return (mv_gpio_value_get(pin) ? 1 : 0);
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}
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static uint32_t
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mv_gpio_reg_read(uint32_t reg)
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{
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return (bus_space_read_4(mv_gpio_softc->bst,
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mv_gpio_softc->bsh, reg));
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}
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static void
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mv_gpio_reg_write(uint32_t reg, uint32_t val)
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{
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bus_space_write_4(mv_gpio_softc->bst,
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mv_gpio_softc->bsh, reg, val);
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}
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static void
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mv_gpio_reg_set(uint32_t reg, uint32_t pin)
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{
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uint32_t reg_val;
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reg_val = mv_gpio_reg_read(reg);
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reg_val |= GPIO(pin);
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mv_gpio_reg_write(reg, reg_val);
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}
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static void
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mv_gpio_reg_clear(uint32_t reg, uint32_t pin)
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{
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uint32_t reg_val;
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reg_val = mv_gpio_reg_read(reg);
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reg_val &= ~(GPIO(pin));
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mv_gpio_reg_write(reg, reg_val);
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}
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static void
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mv_gpio_out_en(uint32_t pin, uint8_t enable)
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{
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uint32_t reg;
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if (pin >= mv_gpio_softc->pin_num)
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return;
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if (pin >= GPIO_PINS_PER_REG) {
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reg = GPIO_HI_DATA_OUT_EN_CTRL;
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pin -= GPIO_PINS_PER_REG;
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} else
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reg = GPIO_DATA_OUT_EN_CTRL;
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if (enable)
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mv_gpio_reg_clear(reg, pin);
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else
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mv_gpio_reg_set(reg, pin);
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}
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static void
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mv_gpio_blink(uint32_t pin, uint8_t enable)
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{
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uint32_t reg;
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if (pin >= mv_gpio_softc->pin_num)
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return;
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if (pin >= GPIO_PINS_PER_REG) {
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reg = GPIO_HI_BLINK_EN;
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pin -= GPIO_PINS_PER_REG;
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} else
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reg = GPIO_BLINK_EN;
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if (enable)
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mv_gpio_reg_set(reg, pin);
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else
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mv_gpio_reg_clear(reg, pin);
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}
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static void
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mv_gpio_polarity(uint32_t pin, uint8_t enable)
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{
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uint32_t reg;
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if (pin >= mv_gpio_softc->pin_num)
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return;
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if (pin >= GPIO_PINS_PER_REG) {
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reg = GPIO_HI_DATA_IN_POLAR;
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pin -= GPIO_PINS_PER_REG;
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} else
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reg = GPIO_DATA_IN_POLAR;
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if (enable)
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mv_gpio_reg_set(reg, pin);
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else
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mv_gpio_reg_clear(reg, pin);
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}
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static void
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mv_gpio_level(uint32_t pin, uint8_t enable)
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{
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uint32_t reg;
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if (pin >= mv_gpio_softc->pin_num)
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return;
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if (pin >= GPIO_PINS_PER_REG) {
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reg = GPIO_HI_INT_LEV_MASK;
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pin -= GPIO_PINS_PER_REG;
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} else
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reg = GPIO_INT_LEV_MASK;
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if (enable)
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mv_gpio_reg_set(reg, pin);
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else
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mv_gpio_reg_clear(reg, pin);
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}
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static void
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mv_gpio_edge(uint32_t pin, uint8_t enable)
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{
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uint32_t reg;
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if (pin >= mv_gpio_softc->pin_num)
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return;
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if (pin >= GPIO_PINS_PER_REG) {
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reg = GPIO_HI_INT_EDGE_MASK;
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pin -= GPIO_PINS_PER_REG;
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} else
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reg = GPIO_INT_EDGE_MASK;
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if (enable)
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mv_gpio_reg_set(reg, pin);
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else
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mv_gpio_reg_clear(reg, pin);
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}
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static void
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mv_gpio_int_ack(uint32_t pin)
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{
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uint32_t reg;
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if (pin >= mv_gpio_softc->pin_num)
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return;
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if (pin >= GPIO_PINS_PER_REG) {
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reg = GPIO_HI_INT_CAUSE;
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pin -= GPIO_PINS_PER_REG;
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} else
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reg = GPIO_INT_CAUSE;
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mv_gpio_reg_clear(reg, pin);
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}
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static uint32_t
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mv_gpio_value_get(uint32_t pin)
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{
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uint32_t reg, reg_val;
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if (pin >= mv_gpio_softc->pin_num)
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return (0);
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if (pin >= GPIO_PINS_PER_REG) {
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reg = GPIO_HI_DATA_IN;
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pin -= GPIO_PINS_PER_REG;
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} else
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reg = GPIO_DATA_IN;
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reg_val = mv_gpio_reg_read(reg);
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return (reg_val & GPIO(pin));
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}
|
|
|
|
static void
|
|
mv_gpio_value_set(uint32_t pin, uint8_t val)
|
|
{
|
|
uint32_t reg;
|
|
|
|
if (pin >= mv_gpio_softc->pin_num)
|
|
return;
|
|
|
|
if (pin >= GPIO_PINS_PER_REG) {
|
|
reg = GPIO_HI_DATA_OUT;
|
|
pin -= GPIO_PINS_PER_REG;
|
|
} else
|
|
reg = GPIO_DATA_OUT;
|
|
|
|
if (val)
|
|
mv_gpio_reg_set(reg, pin);
|
|
else
|
|
mv_gpio_reg_clear(reg, pin);
|
|
}
|
|
|
|
int
|
|
mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len)
|
|
{
|
|
pcell_t gpio_cells, pincnt;
|
|
int inc, t, tuples, tuple_size;
|
|
int dir, flags, pin;
|
|
u_long gpio_ctrl, size;
|
|
struct mv_gpio_softc sc;
|
|
|
|
pincnt = 0;
|
|
if (!OF_hasprop(ctrl, "gpio-controller"))
|
|
/* Node is not a GPIO controller. */
|
|
return (ENXIO);
|
|
|
|
if (OF_getprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0)
|
|
return (ENXIO);
|
|
|
|
gpio_cells = fdt32_to_cpu(gpio_cells);
|
|
if (gpio_cells != 3)
|
|
return (ENXIO);
|
|
|
|
tuple_size = gpio_cells * sizeof(pcell_t) + sizeof(phandle_t);
|
|
tuples = len / tuple_size;
|
|
|
|
if (fdt_regsize(ctrl, &gpio_ctrl, &size))
|
|
return (ENXIO);
|
|
|
|
if (OF_getprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0)
|
|
return (ENXIO);
|
|
sc.pin_num = fdt32_to_cpu(pincnt);
|
|
|
|
/*
|
|
* Skip controller reference, since controller's phandle is given
|
|
* explicitly (in a function argument).
|
|
*/
|
|
inc = sizeof(ihandle_t) / sizeof(pcell_t);
|
|
gpios += inc;
|
|
|
|
for (t = 0; t < tuples; t++) {
|
|
pin = fdt32_to_cpu(gpios[0]);
|
|
dir = fdt32_to_cpu(gpios[1]);
|
|
flags = fdt32_to_cpu(gpios[2]);
|
|
|
|
mv_gpio_configure(pin, flags);
|
|
|
|
if (dir == 1)
|
|
/* Input. */
|
|
mv_gpio_out_en(pin, 0);
|
|
else {
|
|
/* Output. */
|
|
if (flags & MV_GPIO_OUT_OPEN_DRAIN)
|
|
mv_gpio_out(pin, 0, 1);
|
|
|
|
if (flags & MV_GPIO_OUT_OPEN_SRC)
|
|
mv_gpio_out(pin, 1, 1);
|
|
}
|
|
gpios += gpio_cells + inc;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
#define MAX_PINS_PER_NODE 5
|
|
#define GPIOS_PROP_CELLS 4
|
|
static int
|
|
mv_gpio_init(void)
|
|
{
|
|
phandle_t child, parent, root, ctrl;
|
|
pcell_t gpios[MAX_PINS_PER_NODE * GPIOS_PROP_CELLS];
|
|
struct gpio_ctrl_entry *e;
|
|
int len, rv;
|
|
|
|
root = OF_finddevice("/");
|
|
len = 0;
|
|
parent = root;
|
|
|
|
/* Traverse through entire tree to find nodes with 'gpios' prop */
|
|
for (child = OF_child(parent); child != 0; child = OF_peer(child)) {
|
|
|
|
/* Find a 'leaf'. Start the search from this node. */
|
|
while (OF_child(child)) {
|
|
parent = child;
|
|
child = OF_child(child);
|
|
}
|
|
if ((len = OF_getproplen(child, "gpios")) > 0) {
|
|
|
|
if (len > sizeof(gpios))
|
|
return (ENXIO);
|
|
|
|
/* Get 'gpios' property. */
|
|
OF_getprop(child, "gpios", &gpios, len);
|
|
|
|
e = (struct gpio_ctrl_entry *)&gpio_controllers;
|
|
|
|
/* Find and call a handler. */
|
|
for (; e->compat; e++) {
|
|
/*
|
|
* First cell of 'gpios' property should
|
|
* contain a ref. to a node defining GPIO
|
|
* controller.
|
|
*/
|
|
ctrl = OF_node_from_xref(fdt32_to_cpu(gpios[0]));
|
|
|
|
if (fdt_is_compatible(ctrl, e->compat))
|
|
/* Call a handler. */
|
|
if ((rv = e->handler(ctrl,
|
|
(pcell_t *)&gpios, len)))
|
|
return (rv);
|
|
}
|
|
}
|
|
|
|
if (OF_peer(child) == 0) {
|
|
/* No more siblings. */
|
|
child = parent;
|
|
parent = OF_parent(child);
|
|
}
|
|
}
|
|
return (0);
|
|
}
|