John Baldwin 4a9b01b262 Fix EXCP_MASK to include all relevant bits from scause. ... While cause codes higher than 16 are reserved, the exception code field of the register is defined to be all bits but the upper-most bit. Reviewed by: mhorne MFC after: 1 week Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D23510		2020-02-05 20:34:22 +00:00
..
conf	Include the PCI stack to the riscv GENERIC kernel.	2020-01-24 17:10:21 +00:00
include	Fix EXCP_MASK to include all relevant bits from scause.	2020-02-05 20:34:22 +00:00
riscv	Use csr_read() to read sstatus instead of inline assembly.	2020-02-05 20:32:37 +00:00
sifive	prci: register tlclk as a fixed clock	2020-02-01 17:13:52 +00:00