284 lines
12 KiB
C
284 lines
12 KiB
C
/*-
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* Copyright 1992-2016 Michal Meloun
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _TEGRA_HDMI_REG_H_
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#define _TEGRA_HDMI_REG_H_
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/*
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* !!! WARNING !!!
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* Tegra manual uses registers index (and not register addreses).
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* We follow the TRM notation and index is converted to offset in
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* WR4 / RD4 macros
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*/
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#define HDMI_NV_PDISP_SOR_STATE0 0x001
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#define SOR_STATE0_UPDATE (1 << 0)
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#define HDMI_NV_PDISP_SOR_STATE1 0x002
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#define SOR_STATE1_ATTACHED (1 << 3)
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#define SOR_STATE1_ASY_ORMODE_NORMAL (1 << 2)
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#define SOR_STATE1_ASY_HEAD_OPMODE(x) (((x) & 0x3) << 0)
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#define ASY_HEAD_OPMODE_SLEEP 0
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#define ASY_HEAD_OPMODE_SNOOZE 1
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#define ASY_HEAD_OPMODE_AWAKE 2
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#define HDMI_NV_PDISP_SOR_STATE2 0x003
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#define SOR_STATE2_ASY_DEPOL_NEG (1 << 14)
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#define SOR_STATE2_ASY_VSYNCPOL_NEG (1 << 13)
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#define SOR_STATE2_ASY_HSYNCPOL_NEG (1 << 12)
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#define SOR_STATE2_ASY_PROTOCOL(x) (((x) & 0xf) << 8)
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#define ASY_PROTOCOL_SINGLE_TMDS_A 1
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#define ASY_PROTOCOL_CUSTOM 15
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#define SOR_STATE2_ASY_CRCMODE(x) (((x) & 0x3) << 6)
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#define ASY_CRCMODE_ACTIVE 0
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#define ASY_CRCMODE_COMPLETE 1
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#define ASY_CRCMODE_NON_ACTIVE 2
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#define SOR_STATE2_ASY_SUBOWNER(x) (((x) & 0x3) << 4)
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#define ASY_SUBOWNER_NONE 0
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#define ASY_SUBOWNER_SUBHEAD0 1
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#define ASY_SUBOWNER_SUBHEAD1 2
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#define SUBOWNER_BOTH 3
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#define SOR_STATE2_ASY_OWNER(x) (((x) & 0x3) << 0)
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#define ASY_OWNER_NONE 0
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#define ASY_OWNER_HEAD0 1
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x01e
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#define AUDIO_INFOFRAME_CTRL_ENABLE (1 << 0)
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x01f
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x020
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x021
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#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x022
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#define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
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#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
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#define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x023
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#define AVI_INFOFRAME_CTRL_ENABLE (1 << 0)
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x024
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x025
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x026
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x027
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x028
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#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x029
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#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x02a
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#define GENERIC_CTRL_AUDIO (1 << 16)
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#define GENERIC_CTRL_HBLANK (1 << 12)
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#define GENERIC_CTRL_SINGLE (1 << 8)
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#define GENERIC_CTRL_OTHER (1 << 4)
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#define GENERIC_CTRL_ENABLE (1 << 0)
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#define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x02b
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#define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x02c
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x02d
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x02e
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x02f
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x030
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x031
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x032
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x033
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#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x034
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#define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x035
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#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x036
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#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x037
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#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x038
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#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x039
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#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x03a
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#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x03b
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#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x03c
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#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x03d
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#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x03e
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#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x03f
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#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x040
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#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x041
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#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x042
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#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x043
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#define ACR_ENABLE (1U << 31)
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#define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
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#define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)
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#define HDMI_NV_PDISP_HDMI_CTRL 0x044
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#define HDMI_CTRL_ENABLE (1 << 30)
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#define HDMI_CTRL_CA_SELECT (1 << 28)
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#define HDMI_CTRL_SS_SELECT (1 << 27)
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#define HDMI_CTRL_SF_SELECT (1 << 26)
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#define HDMI_CTRL_CC_SELECT (1 << 25)
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#define HDMI_CTRL_CT_SELECT (1 << 24)
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#define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
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#define HDMI_CTRL_SAMPLE_FLAT (1 << 12)
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#define HDMI_CTRL_AUDIO_LAYOUT_SELECT (1 << 10)
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#define HDMI_CTRL_AUDIO_LAYOUT (1 << 8)
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#define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
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#define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x046
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#define VSYNC_WINDOW_ENABLE (1U << 31)
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#define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
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#define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
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#define HDMI_NV_PDISP_HDMI_SPARE 0x04f
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#define SPARE_ACR_PRIORITY (1U << 31)
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#define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
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#define SPARE_SUPRESS_SP_B (1 << 2)
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#define SPARE_FORCE_SW_CTS (1 << 1)
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#define SPARE_HW_CTS (1 << 0)
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#define HDMI_NV_PDISP_SOR_PWR 0x055
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#define SOR_PWR_SETTING_NEW (1U << 31)
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#define SOR_PWR_SAFE_STATE_PU (1 << 16)
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#define SOR_PWR_NORMAL_START_ALT (1 << 1)
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#define SOR_PWR_NORMAL_STATE_PU (1 << 0)
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#define HDMI_NV_PDISP_SOR_PLL0 0x057
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#define SOR_PLL0_TX_REG_LOAD(x) (((x) & 0xf) << 28)
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#define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24)
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#define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16)
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#define SOR_PLL0_BG_V17_S(x) (((x) & 0xf) << 12)
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#define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8)
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#define SOR_PLL0_PULLDOWN (1 << 5)
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#define SOR_PLL0_RESISTORSEL (1 << 4)
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#define SOR_PLL0_PDPORT (1 << 3)
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#define SOR_PLL0_VCOPD (1 << 2)
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#define SOR_PLL0_PDBG (1 << 1)
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#define SOR_PLL0_PWR (1 << 0)
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#define HDMI_NV_PDISP_SOR_PLL1 0x058
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#define SOR_PLL1_S_D_PIN_PE (1 << 30)
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#define SOR_PLL1_HALF_FULL_PE (1 << 29)
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#define SOR_PLL1_PE_EN (1 << 28)
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#define SOR_PLL1_LOADADJ(x) (((x) & 0xf) << 20)
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#define SOR_PLL1_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
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#define SOR_PLL1_TMDS_TERM (1 << 8)
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#define HDMI_NV_PDISP_SOR_CSTM 0x05a
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#define SOR_CSTM_ROTAT(x) (((x) & 0xf) << 28)
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#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
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#define SOR_CSTM_PLLDIV (1 << 21)
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#define SOR_CSTM_BALANCED (1 << 19)
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#define SOR_CSTM_NEW_MODE (1 << 18)
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#define SOR_CSTM_DUP_SYNC (1 << 17)
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#define SOR_CSTM_LVDS_ENABLE (1 << 16)
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#define SOR_CSTM_LINKACTB (1 << 15)
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#define SOR_CSTM_LINKACTA (1 << 14)
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#define SOR_CSTM_MODE(x) (((x) & 0x3) << 12)
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#define CSTM_MODE_LVDS 0
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#define CSTM_MODE_TMDS 1
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#define HDMI_NV_PDISP_SOR_SEQ_CTL 0x05f
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#define SOR_SEQ_SWITCH (1 << 30)
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#define SOR_SEQ_STATUS (1 << 28)
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#define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
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#define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
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#define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
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#define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
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#define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0)
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#define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x060 + (x))
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#define SOR_SEQ_INST_PLL_PULLDOWN (1U << 31)
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#define SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30)
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#define SOR_SEQ_INST_ASSERT_PLL_RESETV (1 << 29)
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#define SOR_SEQ_INST_BLANK_V (1 << 28)
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#define SOR_SEQ_INST_BLANK_H (1 << 27)
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#define SOR_SEQ_INST_BLANK_DE (1 << 26)
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#define SOR_SEQ_INST_BLACK_DATA (1 << 25)
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#define SOR_SEQ_INST_TRISTATE_IOS (1 << 24)
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#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
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#define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
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#define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
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#define SOR_SEQ_INST_HALT (1 << 15)
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#define SOR_SEQ_INST_WAIT_UNITS(x) (((x) & 0x3) << 12)
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#define WAIT_UNITS_US 0
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#define WAIT_UNITS_MS 1
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#define WAIT_UNITS_VSYNC 2
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#define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
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#define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x07e
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#define HDMI_NV_PDISP_AUDIO_N 0x08c
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#define AUDIO_N_LOOKUP (1 << 28)
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#define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
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#define AUDIO_N_RESETF (1 << 20)
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#define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
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#define HDMI_NV_PDISP_SOR_REFCLK 0x095
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#define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
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#define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
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#define HDMI_NV_PDISP_INPUT_CONTROL 0x097
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#define ARM_VIDEO_RANGE_LIMITED (1 << 1)
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#define HDMI_SRC_DISPLAYB (1 << 0)
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#define HDMI_NV_PDISP_PE_CURRENT 0x099
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#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0x0ac
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#define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
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#define SOR_AUDIO_CNTRL0_SOURCE_SELECT(x) (((x) & 0x03) << 20)
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#define SOURCE_SELECT_AUTO 0
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#define SOURCE_SELECT_SPDIF 1
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#define SOURCE_SELECT_HDAL 2
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#define SOR_AUDIO_CNTRL0_AFIFO_FLUSH (1 << 12)
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#define HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0x0ae
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#define SOR_AUDIO_SPARE0_HBR_ENABLE (1 << 27)
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#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0320 0x0af
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#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0441 0x0b0
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#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0882 0x0b1
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#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1764 0x0b2
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#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0480 0x0b3
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#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0960 0x0b4
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#define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1920 0x0b5
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#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0 0x0b6
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#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1 0x0b7
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#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2 0x0b8
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#define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3 0x0b9
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#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0x0ba
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#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1 0x0bb
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#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0x0bc
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#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0x0bd
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#define SOR_AUDIO_HDA_PRESENSE_VALID (1 << 1)
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#define SOR_AUDIO_HDA_PRESENSE_PRESENT (1 << 0)
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0x0bf
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0x0c0
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0x0c1
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0x0c2
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0x0c3
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0x0c4
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0x0c5
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#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0x0c6
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#define HDMI_NV_PDISP_INT_STATUS 0x0cc
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#define INT_SCRATCH (1 << 3)
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#define INT_CP_REQUEST (1 << 2)
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#define INT_CODEC_SCRATCH1 (1 << 1)
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#define INT_CODEC_SCRATCH0 (1 << 0)
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#define HDMI_NV_PDISP_INT_MASK 0x0cd
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#define HDMI_NV_PDISP_INT_ENABLE 0x0ce
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#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0x0d1
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#define HDMI_NV_PDISP_SOR_PAD_CTLS0 0x0d2
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#endif /* _TEGRA_HDMI_REG_H_ */
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