592 lines
15 KiB
C
592 lines
15 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/nvidia/tegra_efuse.h>
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#include "cpufreq_if.h"
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#define XXX
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/* CPU voltage table entry */
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struct speedo_entry {
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uint64_t freq; /* Frequency point */
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int c0; /* Coeeficient values for */
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int c1; /* quadratic equation: */
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int c2; /* c2 * speedo^2 + c1 * speedo + c0 */
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};
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struct cpu_volt_def {
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int min_uvolt; /* Min allowed CPU voltage */
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int max_uvolt; /* Max allowed CPU voltage */
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int step_uvolt; /* Step of CPU voltage */
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int speedo_scale; /* Scaling factor for cvt */
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int speedo_nitems; /* Size of speedo table */
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struct speedo_entry *speedo_tbl; /* CPU voltage table */
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};
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struct cpu_speed_point {
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uint64_t freq; /* Frequecy */
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int uvolt; /* Requested voltage */
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};
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static struct speedo_entry tegra124_speedo_dpll_tbl[] =
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{
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{ 204000000ULL, 1112619, -29295, 402},
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{ 306000000ULL, 1150460, -30585, 402},
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{ 408000000ULL, 1190122, -31865, 402},
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{ 510000000ULL, 1231606, -33155, 402},
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{ 612000000ULL, 1274912, -34435, 402},
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{ 714000000ULL, 1320040, -35725, 402},
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{ 816000000ULL, 1366990, -37005, 402},
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{ 918000000ULL, 1415762, -38295, 402},
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{1020000000ULL, 1466355, -39575, 402},
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{1122000000ULL, 1518771, -40865, 402},
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{1224000000ULL, 1573009, -42145, 402},
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{1326000000ULL, 1629068, -43435, 402},
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{1428000000ULL, 1686950, -44715, 402},
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{1530000000ULL, 1746653, -46005, 402},
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{1632000000ULL, 1808179, -47285, 402},
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{1734000000ULL, 1871526, -48575, 402},
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{1836000000ULL, 1936696, -49855, 402},
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{1938000000ULL, 2003687, -51145, 402},
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{2014500000ULL, 2054787, -52095, 402},
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{2116500000ULL, 2124957, -53385, 402},
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{2218500000ULL, 2196950, -54665, 402},
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{2320500000ULL, 2270765, -55955, 402},
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{2320500000ULL, 2270765, -55955, 402},
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{2422500000ULL, 2346401, -57235, 402},
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{2524500000ULL, 2437299, -58535, 402},
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};
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static struct cpu_volt_def tegra124_cpu_volt_dpll_def =
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{
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.min_uvolt = 900000, /* 0.9 V */
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.max_uvolt = 1260000, /* 1.26 */
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.step_uvolt = 10000, /* 10 mV */
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.speedo_scale = 100,
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.speedo_nitems = nitems(tegra124_speedo_dpll_tbl),
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.speedo_tbl = tegra124_speedo_dpll_tbl,
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};
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static struct speedo_entry tegra124_speedo_pllx_tbl[] =
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{
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{ 204000000ULL, 800000, 0, 0},
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{ 306000000ULL, 800000, 0, 0},
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{ 408000000ULL, 800000, 0, 0},
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{ 510000000ULL, 800000, 0, 0},
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{ 612000000ULL, 800000, 0, 0},
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{ 714000000ULL, 800000, 0, 0},
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{ 816000000ULL, 820000, 0, 0},
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{ 918000000ULL, 840000, 0, 0},
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{1020000000ULL, 880000, 0, 0},
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{1122000000ULL, 900000, 0, 0},
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{1224000000ULL, 930000, 0, 0},
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{1326000000ULL, 960000, 0, 0},
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{1428000000ULL, 990000, 0, 0},
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{1530000000ULL, 1020000, 0, 0},
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{1632000000ULL, 1070000, 0, 0},
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{1734000000ULL, 1100000, 0, 0},
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{1836000000ULL, 1140000, 0, 0},
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{1938000000ULL, 1180000, 0, 0},
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{2014500000ULL, 1220000, 0, 0},
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{2116500000ULL, 1260000, 0, 0},
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{2218500000ULL, 1310000, 0, 0},
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{2320500000ULL, 1360000, 0, 0},
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{2397000000ULL, 1400000, 0, 0},
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{2499000000ULL, 1400000, 0, 0},
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};
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static struct cpu_volt_def tegra124_cpu_volt_pllx_def =
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{
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.min_uvolt = 1000000, /* XXX 0.9 V doesn't work on all boards */
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.max_uvolt = 1260000, /* 1.26 */
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.step_uvolt = 10000, /* 10 mV */
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.speedo_scale = 100,
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.speedo_nitems = nitems(tegra124_speedo_pllx_tbl),
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.speedo_tbl = tegra124_speedo_pllx_tbl,
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};
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static uint64_t cpu_freq_tbl[] = {
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204000000ULL,
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306000000ULL,
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408000000ULL,
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510000000ULL,
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612000000ULL,
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714000000ULL,
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816000000ULL,
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918000000ULL,
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1020000000ULL,
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1122000000ULL,
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1224000000ULL,
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1326000000ULL,
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1428000000ULL,
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1530000000ULL,
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1632000000ULL,
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1734000000ULL,
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1836000000ULL,
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1938000000ULL,
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2014000000ULL,
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2116000000ULL,
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2218000000ULL,
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2320000000ULL,
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2422000000ULL,
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2524000000ULL,
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};
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static uint64_t cpu_max_freq[] = {
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2014500000ULL,
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2320500000ULL,
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2116500000ULL,
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2524500000ULL,
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};
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struct tegra124_cpufreq_softc {
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device_t dev;
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phandle_t node;
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regulator_t supply_vdd_cpu;
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clk_t clk_cpu_g;
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clk_t clk_cpu_lp;
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clk_t clk_pll_x;
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clk_t clk_pll_p;
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clk_t clk_dfll;
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int process_id;
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int speedo_id;
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int speedo_value;
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uint64_t cpu_max_freq;
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struct cpu_volt_def *cpu_def;
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struct cpu_speed_point *speed_points;
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int nspeed_points;
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struct cpu_speed_point *act_speed_point;
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int latency;
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};
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static int cpufreq_lowest_freq = 1;
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TUNABLE_INT("hw.tegra124.cpufreq.lowest_freq", &cpufreq_lowest_freq);
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#define DIV_ROUND_CLOSEST(val, div) (((val) + ((div) / 2)) / (div))
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#define ROUND_UP(val, div) roundup(val, div)
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#define ROUND_DOWN(val, div) rounddown(val, div)
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/*
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* Compute requesetd voltage for given frequency and SoC process variations,
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* - compute base voltage from speedo value using speedo table
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* - round up voltage to next regulator step
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* - clamp it to regulator limits
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*/
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static int
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freq_to_voltage(struct tegra124_cpufreq_softc *sc, uint64_t freq)
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{
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int uv, scale, min_uvolt, max_uvolt, step_uvolt;
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struct speedo_entry *ent;
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int i;
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/* Get speedo entry with higher frequency */
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ent = NULL;
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for (i = 0; i < sc->cpu_def->speedo_nitems; i++) {
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if (sc->cpu_def->speedo_tbl[i].freq >= freq) {
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ent = &sc->cpu_def->speedo_tbl[i];
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break;
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}
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}
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if (ent == NULL)
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ent = &sc->cpu_def->speedo_tbl[sc->cpu_def->speedo_nitems - 1];
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scale = sc->cpu_def->speedo_scale;
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/* uV = (c2 * speedo / scale + c1) * speedo / scale + c0) */
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uv = DIV_ROUND_CLOSEST(ent->c2 * sc->speedo_value, scale);
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uv = DIV_ROUND_CLOSEST((uv + ent->c1) * sc->speedo_value, scale) +
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ent->c0;
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step_uvolt = sc->cpu_def->step_uvolt;
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/* Round up it to next regulator step */
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uv = ROUND_UP(uv, step_uvolt);
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/* Clamp result */
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min_uvolt = ROUND_UP(sc->cpu_def->min_uvolt, step_uvolt);
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max_uvolt = ROUND_DOWN(sc->cpu_def->max_uvolt, step_uvolt);
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if (uv < min_uvolt)
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uv = min_uvolt;
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if (uv > max_uvolt)
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uv = max_uvolt;
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return (uv);
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}
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static void
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build_speed_points(struct tegra124_cpufreq_softc *sc) {
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int i;
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sc->nspeed_points = nitems(cpu_freq_tbl);
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sc->speed_points = malloc(sizeof(struct cpu_speed_point) *
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sc->nspeed_points, M_DEVBUF, M_NOWAIT);
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for (i = 0; i < sc->nspeed_points; i++) {
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sc->speed_points[i].freq = cpu_freq_tbl[i];
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sc->speed_points[i].uvolt = freq_to_voltage(sc,
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cpu_freq_tbl[i]);
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}
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}
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static struct cpu_speed_point *
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get_speed_point(struct tegra124_cpufreq_softc *sc, uint64_t freq)
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{
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int i;
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if (sc->speed_points[0].freq >= freq)
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return (sc->speed_points + 0);
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for (i = 0; i < sc->nspeed_points - 1; i++) {
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if (sc->speed_points[i + 1].freq > freq)
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return (sc->speed_points + i);
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}
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return (sc->speed_points + sc->nspeed_points - 1);
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}
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static int
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tegra124_cpufreq_settings(device_t dev, struct cf_setting *sets, int *count)
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{
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struct tegra124_cpufreq_softc *sc;
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int i, j;
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if (sets == NULL || count == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * (*count));
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for (i = 0, j = sc->nspeed_points - 1; j >= 0; j--) {
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if (sc->cpu_max_freq < sc->speed_points[j].freq)
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continue;
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sets[i].freq = sc->speed_points[j].freq / 1000000;
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sets[i].volts = sc->speed_points[j].uvolt / 1000;
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sets[i].lat = sc->latency;
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sets[i].dev = dev;
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i++;
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}
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*count = i;
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return (0);
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}
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static int
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set_cpu_freq(struct tegra124_cpufreq_softc *sc, uint64_t freq)
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{
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struct cpu_speed_point *point;
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int rv;
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point = get_speed_point(sc, freq);
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if (sc->act_speed_point->uvolt < point->uvolt) {
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/* set cpu voltage */
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rv = regulator_set_voltage(sc->supply_vdd_cpu,
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point->uvolt, point->uvolt);
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DELAY(10000);
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if (rv != 0)
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return (rv);
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}
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/* Switch supermux to PLLP first */
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rv = clk_set_parent_by_clk(sc->clk_cpu_g, sc->clk_pll_p);
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if (rv != 0) {
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device_printf(sc->dev, "Can't set parent to PLLP\n");
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return (rv);
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}
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/* Set PLLX frequency */
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rv = clk_set_freq(sc->clk_pll_x, point->freq, CLK_SET_ROUND_DOWN);
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if (rv != 0) {
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device_printf(sc->dev, "Can't set CPU clock frequency\n");
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return (rv);
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}
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rv = clk_set_parent_by_clk(sc->clk_cpu_g, sc->clk_pll_x);
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if (rv != 0) {
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device_printf(sc->dev, "Can't set parent to PLLX\n");
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return (rv);
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}
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if (sc->act_speed_point->uvolt > point->uvolt) {
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/* set cpu voltage */
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rv = regulator_set_voltage(sc->supply_vdd_cpu,
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point->uvolt, point->uvolt);
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if (rv != 0)
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return (rv);
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}
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sc->act_speed_point = point;
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return (0);
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}
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static int
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tegra124_cpufreq_set(device_t dev, const struct cf_setting *cf)
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{
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struct tegra124_cpufreq_softc *sc;
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uint64_t freq;
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int rv;
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if (cf == NULL || cf->freq < 0)
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return (EINVAL);
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sc = device_get_softc(dev);
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freq = cf->freq;
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if (freq < cpufreq_lowest_freq)
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freq = cpufreq_lowest_freq;
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freq *= 1000000;
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if (freq >= sc->cpu_max_freq)
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freq = sc->cpu_max_freq;
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rv = set_cpu_freq(sc, freq);
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return (rv);
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}
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static int
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tegra124_cpufreq_get(device_t dev, struct cf_setting *cf)
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{
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struct tegra124_cpufreq_softc *sc;
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if (cf == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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memset(cf, CPUFREQ_VAL_UNKNOWN, sizeof(*cf));
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cf->dev = NULL;
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cf->freq = sc->act_speed_point->freq / 1000000;
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cf->volts = sc->act_speed_point->uvolt / 1000;
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/* Transition latency in us. */
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cf->lat = sc->latency;
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/* Driver providing this setting. */
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cf->dev = dev;
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return (0);
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}
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static int
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tegra124_cpufreq_type(device_t dev, int *type)
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{
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if (type == NULL)
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return (EINVAL);
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*type = CPUFREQ_TYPE_ABSOLUTE;
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return (0);
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}
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static int
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get_fdt_resources(struct tegra124_cpufreq_softc *sc, phandle_t node)
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{
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int rv;
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device_t parent_dev;
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parent_dev = device_get_parent(sc->dev);
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rv = regulator_get_by_ofw_property(parent_dev, 0, "vdd-cpu-supply",
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&sc->supply_vdd_cpu);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'vdd-cpu' regulator\n");
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return (rv);
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}
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rv = clk_get_by_ofw_name(parent_dev, 0, "cpu_g", &sc->clk_cpu_g);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'cpu_g' clock: %d\n", rv);
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return (ENXIO);
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}
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rv = clk_get_by_ofw_name(parent_dev, 0, "cpu_lp", &sc->clk_cpu_lp);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'cpu_lp' clock\n");
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return (ENXIO);
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}
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rv = clk_get_by_ofw_name(parent_dev, 0, "pll_x", &sc->clk_pll_x);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'pll_x' clock\n");
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return (ENXIO);
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}
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rv = clk_get_by_ofw_name(parent_dev, 0, "pll_p", &sc->clk_pll_p);
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if (rv != 0) {
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device_printf(parent_dev, "Cannot get 'pll_p' clock\n");
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return (ENXIO);
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}
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rv = clk_get_by_ofw_name(parent_dev, 0, "dfll", &sc->clk_dfll);
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if (rv != 0) {
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/* XXX DPLL is not implemented yet */
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/*
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device_printf(sc->dev, "Cannot get 'dfll' clock\n");
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return (ENXIO);
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*/
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}
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return (0);
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}
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static void
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tegra124_cpufreq_identify(driver_t *driver, device_t parent)
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{
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phandle_t root;
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root = OF_finddevice("/");
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if (!ofw_bus_node_is_compatible(root, "nvidia,tegra124"))
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return;
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if (device_get_unit(parent) != 0)
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return;
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if (device_find_child(parent, "tegra124_cpufreq", -1) != NULL)
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return;
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if (BUS_ADD_CHILD(parent, 0, "tegra124_cpufreq", -1) == NULL)
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device_printf(parent, "add child failed\n");
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}
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static int
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tegra124_cpufreq_probe(device_t dev)
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{
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device_set_desc(dev, "CPU Frequency Control");
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra124_cpufreq_attach(device_t dev)
|
|
{
|
|
struct tegra124_cpufreq_softc *sc;
|
|
uint64_t freq;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
sc->node = ofw_bus_get_node(device_get_parent(dev));
|
|
|
|
sc->process_id = tegra_sku_info.cpu_process_id;
|
|
sc->speedo_id = tegra_sku_info.cpu_speedo_id;
|
|
sc->speedo_value = tegra_sku_info.cpu_speedo_value;
|
|
|
|
/* Tegra 124 */
|
|
/* XXX DPLL is not implemented yet */
|
|
if (1)
|
|
sc->cpu_def = &tegra124_cpu_volt_pllx_def;
|
|
else
|
|
sc->cpu_def = &tegra124_cpu_volt_dpll_def;
|
|
|
|
rv = get_fdt_resources(sc, sc->node);
|
|
if (rv != 0) {
|
|
return (rv);
|
|
}
|
|
|
|
build_speed_points(sc);
|
|
|
|
rv = clk_get_freq(sc->clk_cpu_g, &freq);
|
|
if (rv != 0) {
|
|
device_printf(dev, "Can't get CPU clock frequency\n");
|
|
return (rv);
|
|
}
|
|
if (sc->speedo_id < nitems(cpu_max_freq))
|
|
sc->cpu_max_freq = cpu_max_freq[sc->speedo_id];
|
|
else
|
|
sc->cpu_max_freq = cpu_max_freq[0];
|
|
sc->act_speed_point = get_speed_point(sc, freq);
|
|
|
|
/* Set safe startup CPU frequency. */
|
|
rv = set_cpu_freq(sc, 1632000000);
|
|
if (rv != 0) {
|
|
device_printf(dev, "Can't set initial CPU clock frequency\n");
|
|
return (rv);
|
|
}
|
|
|
|
/* This device is controlled by cpufreq(4). */
|
|
cpufreq_register(dev);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra124_cpufreq_detach(device_t dev)
|
|
{
|
|
struct tegra124_cpufreq_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
cpufreq_unregister(dev);
|
|
|
|
if (sc->supply_vdd_cpu != NULL)
|
|
regulator_release(sc->supply_vdd_cpu);
|
|
|
|
if (sc->clk_cpu_g != NULL)
|
|
clk_release(sc->clk_cpu_g);
|
|
if (sc->clk_cpu_lp != NULL)
|
|
clk_release(sc->clk_cpu_lp);
|
|
if (sc->clk_pll_x != NULL)
|
|
clk_release(sc->clk_pll_x);
|
|
if (sc->clk_pll_p != NULL)
|
|
clk_release(sc->clk_pll_p);
|
|
if (sc->clk_dfll != NULL)
|
|
clk_release(sc->clk_dfll);
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t tegra124_cpufreq_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_identify, tegra124_cpufreq_identify),
|
|
DEVMETHOD(device_probe, tegra124_cpufreq_probe),
|
|
DEVMETHOD(device_attach, tegra124_cpufreq_attach),
|
|
DEVMETHOD(device_detach, tegra124_cpufreq_detach),
|
|
|
|
/* cpufreq interface */
|
|
DEVMETHOD(cpufreq_drv_set, tegra124_cpufreq_set),
|
|
DEVMETHOD(cpufreq_drv_get, tegra124_cpufreq_get),
|
|
DEVMETHOD(cpufreq_drv_settings, tegra124_cpufreq_settings),
|
|
DEVMETHOD(cpufreq_drv_type, tegra124_cpufreq_type),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static DEFINE_CLASS_0(tegra124_cpufreq, tegra124_cpufreq_driver,
|
|
tegra124_cpufreq_methods, sizeof(struct tegra124_cpufreq_softc));
|
|
DRIVER_MODULE(tegra124_cpufreq, cpu, tegra124_cpufreq_driver, NULL, NULL);
|