6527b9baef
Ampere Altra in a dual socket configuration has 12 ITSes for the 12 PCIe root complexes. The NIRQ interrupts are statically split between each child of the gic bus, so here we increase that value. 16k is enough for (#cpus * #its * max_pcie_bifurcation) LPIs + (#SPIs and #PPIs) Reviewed by: jhb Approved by: scottl (implicit) MFC after: 1 week Sponsored by: Ampere Computing Differential Revision: https://reviews.freebsd.org/D26766
58 lines
1.8 KiB
C
58 lines
1.8 KiB
C
/*-
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* Copyright (c) 2014 Andrew Turner <andrew@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_INTR_H_
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#define _MACHINE_INTR_H_
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#ifdef FDT
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#include <dev/ofw/openfirm.h>
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#endif
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#include <sys/intr.h>
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#ifndef NIRQ
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#define NIRQ 16384 /* XXX - It should be an option. */
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#endif
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static inline void
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arm_irq_memory_barrier(uintptr_t irq)
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{
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}
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#ifdef SMP
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void intr_ipi_dispatch(u_int, struct trapframe *);
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#endif
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#ifdef DEV_ACPI
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#define ACPI_INTR_XREF 1
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#define ACPI_MSI_XREF 2
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#define ACPI_GPIO_XREF 3
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#endif
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#endif /* _MACHINE_INTR_H */
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