a6ffc42f7a
we have both the Amlogic pic and a GIC. This may be the case in some configurations. Differential Revision: https://reviews.freebsd.org/D2432 Submitted by: John Wehle <john@feith.com>
279 lines
6.9 KiB
C
279 lines
6.9 KiB
C
/*-
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* Copyright 2013-2015 John Wehle <john@feith.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Amlogic aml8726 PIC driver.
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*
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* The current implementation doesn't include support for FIQ.
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*
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* There is a set of four interrupt controllers per cpu located in adjacent
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* memory addresses (the set for cpu 1 starts right after the set for cpu 0)
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* ... this allows for interrupt handling to be spread across the cpus.
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*
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* The multicore chips also have a GIC ... typically they run SMP kernels
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* which include the GIC driver in which case this driver is simply used
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* to disable the PIC.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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struct aml8726_pic_softc {
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device_t dev;
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struct resource * res[1];
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};
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static struct resource_spec aml8726_pic_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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/*
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* devclass_get_device / device_get_softc could be used
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* to dynamically locate this, however the pic is a
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* required device which can't be unloaded so there's
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* no need for the overhead.
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*/
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static struct aml8726_pic_softc *aml8726_pic_sc = NULL;
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#define AML_PIC_NCNTRLS 4
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#define AML_PIC_IRQS_PER_CNTRL 32
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#define AML_PIC_NIRQS (AML_PIC_NCNTRLS * AML_PIC_IRQS_PER_CNTRL)
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#define AML_PIC_0_STAT_REG 0
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#define AML_PIC_0_STAT_CLR_REG 4
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#define AML_PIC_0_MASK_REG 8
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#define AML_PIC_0_FIRQ_SEL 12
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#define AML_PIC_1_STAT_REG 16
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#define AML_PIC_1_STAT_CLR_REG 20
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#define AML_PIC_1_MASK_REG 24
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#define AML_PIC_1_FIRQ_SEL 28
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#define AML_PIC_2_STAT_REG 32
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#define AML_PIC_2_STAT_CLR_REG 36
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#define AML_PIC_2_MASK_REG 40
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#define AML_PIC_2_FIRQ_SEL 44
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#define AML_PIC_3_STAT_REG 48
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#define AML_PIC_3_STAT_CLR_REG 52
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#define AML_PIC_3_MASK_REG 56
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#define AML_PIC_3_FIRQ_SEL 60
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#define AML_PIC_CTRL(x) ((x) >> 5)
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#define AML_PIC_BIT(x) (1 << ((x) & 0x1f))
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#define AML_PIC_STAT_REG(x) (AML_PIC_0_STAT_REG + AML_PIC_CTRL(x) * 16)
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#define AML_PIC_STAT_CLR_REG(x) (AML_PIC_0_STAT_CLR_REG + AML_PIC_CTRL(x) * 16)
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#define AML_PIC_MASK_REG(x) (AML_PIC_0_MASK_REG + AML_PIC_CTRL(x) * 16)
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#define AML_PIC_FIRQ_SEL(x) (AML_PIC_0_FIRQ_REG + AML_PIC_CTRL(x) * 16)
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#define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
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#define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
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#define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
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(BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
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static void
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aml8726_pic_eoi(void *arg)
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{
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uintptr_t nb = (uintptr_t) arg;
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if (nb >= AML_PIC_NIRQS)
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return;
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arm_irq_memory_barrier(nb);
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CSR_WRITE_4(aml8726_pic_sc, AML_PIC_STAT_CLR_REG(nb), AML_PIC_BIT(nb));
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CSR_BARRIER(aml8726_pic_sc, AML_PIC_STAT_CLR_REG(nb));
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}
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static int
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aml8726_pic_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-pic"))
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return (ENXIO);
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device_set_desc(dev, "Amlogic aml8726 PIC");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aml8726_pic_attach(device_t dev)
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{
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struct aml8726_pic_softc *sc = device_get_softc(dev);
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int i;
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/* There should be exactly one instance. */
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if (aml8726_pic_sc != NULL)
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return (ENXIO);
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sc->dev = dev;
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if (bus_alloc_resources(dev, aml8726_pic_spec, sc->res)) {
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device_printf(dev, "could not allocate resources for device\n");
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return (ENXIO);
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}
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/*
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* Disable, clear, and set the interrupts to normal mode.
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*/
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for (i = 0; i < AML_PIC_NCNTRLS; i++) {
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CSR_WRITE_4(sc, AML_PIC_0_MASK_REG + i * 16, 0);
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CSR_WRITE_4(sc, AML_PIC_0_STAT_CLR_REG + i * 16, ~0u);
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CSR_WRITE_4(sc, AML_PIC_0_FIRQ_SEL + i * 16, 0);
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}
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#ifndef DEV_GIC
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arm_post_filter = aml8726_pic_eoi;
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#else
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device_printf(dev, "disabled in favor of gic\n");
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#endif
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aml8726_pic_sc = sc;
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return (0);
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}
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static int
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aml8726_pic_detach(device_t dev)
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{
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return (EBUSY);
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}
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static device_method_t aml8726_pic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, aml8726_pic_probe),
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DEVMETHOD(device_attach, aml8726_pic_attach),
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DEVMETHOD(device_detach, aml8726_pic_detach),
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DEVMETHOD_END
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};
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static driver_t aml8726_pic_driver = {
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"pic",
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aml8726_pic_methods,
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sizeof(struct aml8726_pic_softc),
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};
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static devclass_t aml8726_pic_devclass;
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EARLY_DRIVER_MODULE(pic, simplebus, aml8726_pic_driver, aml8726_pic_devclass,
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0, 0, BUS_PASS_INTERRUPT);
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#ifndef DEV_GIC
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int
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arm_get_next_irq(int last)
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{
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uint32_t value;
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int irq;
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int start;
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/*
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* The extra complexity is simply so that all IRQs are checked
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* round robin so a particularly busy interrupt can't prevent
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* other interrupts from being serviced.
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*/
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start = (last + 1) % AML_PIC_NIRQS;
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irq = start;
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for ( ; ; ) {
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value = CSR_READ_4(aml8726_pic_sc, AML_PIC_STAT_REG(irq));
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for ( ; ; ) {
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if ((value & AML_PIC_BIT(irq)) != 0)
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return (irq);
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irq = (irq + 1) % AML_PIC_NIRQS;
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if (irq == start)
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return (-1);
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if ((irq % AML_PIC_IRQS_PER_CNTRL) == 0)
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break;
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}
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}
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}
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void
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arm_mask_irq(uintptr_t nb)
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{
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uint32_t mask;
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if (nb >= AML_PIC_NIRQS)
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return;
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mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
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mask &= ~AML_PIC_BIT(nb);
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CSR_WRITE_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb), mask);
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CSR_BARRIER(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
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aml8726_pic_eoi((void *)nb);
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}
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void
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arm_unmask_irq(uintptr_t nb)
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{
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uint32_t mask;
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if (nb >= AML_PIC_NIRQS)
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return;
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arm_irq_memory_barrier(nb);
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mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
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mask |= AML_PIC_BIT(nb);
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CSR_WRITE_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb), mask);
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CSR_BARRIER(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
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}
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#endif
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