1310 lines
30 KiB
C
1310 lines
30 KiB
C
/* $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $ */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/* $NetBSD$ */
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#define CT_DEBUG
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#define CT_IO_CONTROL_FLAGS (CT_USE_CCSEQ | CT_FAST_INTR)
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/*
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* [NetBSD for NEC PC-98 series]
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* Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
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* NetBSD/pc98 porting staff. All rights reserved.
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*
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* Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
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* Naofumi HONDA. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#if defined(__FreeBSD__) && __FreeBSD_version > 500001
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#include <sys/bio.h>
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#endif /* __ FreeBSD__ */
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#include <sys/buf.h>
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#include <sys/queue.h>
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#include <sys/malloc.h>
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#include <sys/errno.h>
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#ifdef __NetBSD__
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_disk.h>
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#include <machine/dvcfg.h>
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#include <machine/physio_proc.h>
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#include <i386/Cbus/dev/scsi_low.h>
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#include <dev/ic/wd33c93reg.h>
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#include <i386/Cbus/dev/ct/ctvar.h>
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#include <i386/Cbus/dev/ct/ct_machdep.h>
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#endif /* __NetBSD__ */
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#ifdef __FreeBSD__
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#include <machine/bus.h>
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#include <compat/netbsd/dvcfg.h>
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#include <compat/netbsd/physio_proc.h>
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#include <cam/scsi/scsi_low.h>
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#include <dev/ic/wd33c93reg.h>
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#include <dev/ct/ctvar.h>
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#include <dev/ct/ct_machdep.h>
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#endif /* __FreeBSD__ */
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#define CT_NTARGETS 8
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#define CT_NLUNS 8
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#define CT_RESET_DEFAULT 2000
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#define CT_DELAY_MAX (2 * 1000 * 1000)
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#define CT_DELAY_INTERVAL (1)
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/***************************************************
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* DEBUG
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***************************************************/
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#ifdef CT_DEBUG
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int ct_debug;
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#endif /* CT_DEBUG */
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/***************************************************
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* IO control
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***************************************************/
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#define CT_USE_CCSEQ 0x0100
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#define CT_FAST_INTR 0x0200
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u_int ct_io_control = CT_IO_CONTROL_FLAGS;
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/***************************************************
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* default data
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***************************************************/
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u_int8_t cthw_cmdlevel[256] = {
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/* 0 1 2 3 4 5 6 7 8 9 A B C E D F */
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/*0*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
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/*1*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
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/*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*4*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*5*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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/*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
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};
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#if 0
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/* default synch data table */
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/* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */
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/* X 100 150 200 250 300 350 400 500 ns */
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static struct ct_synch_data ct_synch_data_FSCSI[] = {
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{25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30},
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{87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0}
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};
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static struct ct_synch_data ct_synch_data_SCSI[] = {
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{50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0}
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};
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#endif
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/***************************************************
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* DEVICE STRUCTURE
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***************************************************/
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extern struct cfdriver ct_cd;
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/*****************************************************************
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* Interface functions
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*****************************************************************/
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static int ct_xfer(struct ct_softc *, u_int8_t *, int, int, u_int *);
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static void ct_io_xfer(struct ct_softc *);
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static int ct_reselected(struct ct_softc *, u_int8_t);
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static void ct_phase_error(struct ct_softc *, u_int8_t);
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static int ct_start_selection(struct ct_softc *, struct slccb *);
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static int ct_msg(struct ct_softc *, struct targ_info *, u_int);
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static int ct_world_start(struct ct_softc *, int);
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static __inline void cthw_phase_bypass(struct ct_softc *, u_int8_t);
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static int cthw_chip_reset(struct ct_bus_access_handle *, int *, int, int);
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static void cthw_bus_reset(struct ct_softc *);
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static int ct_ccb_nexus_establish(struct ct_softc *);
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static int ct_lun_nexus_establish(struct ct_softc *);
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static int ct_target_nexus_establish(struct ct_softc *, int, int);
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static void cthw_attention(struct ct_softc *);
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static int ct_targ_init(struct ct_softc *, struct targ_info *, int);
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static int ct_unbusy(struct ct_softc *);
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static void ct_attention(struct ct_softc *);
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static struct ct_synch_data *ct_make_synch_table(struct ct_softc *);
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static int ct_catch_intr(struct ct_softc *);
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struct scsi_low_funcs ct_funcs = {
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SC_LOW_INIT_T ct_world_start,
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SC_LOW_BUSRST_T cthw_bus_reset,
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SC_LOW_TARG_INIT_T ct_targ_init,
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SC_LOW_LUN_INIT_T NULL,
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SC_LOW_SELECT_T ct_start_selection,
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SC_LOW_NEXUS_T ct_lun_nexus_establish,
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SC_LOW_NEXUS_T ct_ccb_nexus_establish,
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SC_LOW_ATTEN_T cthw_attention,
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SC_LOW_MSG_T ct_msg,
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SC_LOW_TIMEOUT_T NULL,
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SC_LOW_POLL_T ctintr,
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NULL, /* SC_LOW_POWER_T cthw_power, */
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};
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/**************************************************
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* HW functions
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**************************************************/
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static __inline void
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cthw_phase_bypass(ct, ph)
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struct ct_softc *ct;
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u_int8_t ph;
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{
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struct ct_bus_access_handle *chp = &ct->sc_ch;
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ct_cr_write_1(chp, wd3s_cph, ph);
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ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR);
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}
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static void
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cthw_bus_reset(ct)
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struct ct_softc *ct;
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{
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/*
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* wd33c93 does not have bus reset function.
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*/
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if (ct->ct_bus_reset != NULL)
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((*ct->ct_bus_reset) (ct));
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}
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static int
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cthw_chip_reset(chp, chiprevp, chipclk, hostid)
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struct ct_bus_access_handle *chp;
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int *chiprevp;
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int chipclk, hostid;
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{
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#define CT_SELTIMEOUT_20MHz_REGV (0x80)
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u_int8_t aux, regv;
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u_int seltout;
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int wc;
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/* issue abort cmd */
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ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT);
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SCSI_LOW_DELAY(1000); /* 1ms wait */
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(void) ct_stat_read_1(chp);
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(void) ct_cr_read_1(chp, wd3s_stat);
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/* setup chip registers */
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regv = 0;
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seltout = CT_SELTIMEOUT_20MHz_REGV;
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switch (chipclk)
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{
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case 8:
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case 10:
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seltout = (seltout * chipclk) / 20;
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regv = IDR_FS_8_10;
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break;
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case 12:
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case 15:
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seltout = (seltout * chipclk) / 20;
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regv = IDR_FS_12_15;
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break;
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case 16:
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case 20:
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seltout = (seltout * chipclk) / 20;
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regv = IDR_FS_16_20;
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break;
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default:
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panic("ct: illegal chip clk rate");
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break;
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}
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regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF;
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ct_cr_write_1(chp, wd3s_oid, regv);
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ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
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for (wc = CT_RESET_DEFAULT; wc > 0; wc --)
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{
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aux = ct_stat_read_1(chp);
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if (aux != 0xff && (aux & STR_INT))
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{
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regv = ct_cr_read_1(chp, wd3s_stat);
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if (regv == BSR_RESET || regv == BSR_AFM_RESET)
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break;
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ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
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}
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SCSI_LOW_DELAY(1);
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}
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if (wc == 0)
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return ENXIO;
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ct_cr_write_1(chp, wd3s_tout, seltout);
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ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL);
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ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT);
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ct_cr_write_1(chp, wd3s_synch, 0);
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if (chiprevp != NULL)
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{
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*chiprevp = CT_WD33C93;
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if (regv == BSR_RESET)
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goto out;
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*chiprevp = CT_WD33C93_A;
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ct_cr_write_1(chp, wd3s_qtag, 0xaa);
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if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa)
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{
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ct_cr_write_1(chp, wd3s_qtag, 0x0);
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goto out;
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}
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ct_cr_write_1(chp, wd3s_qtag, 0x55);
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if (ct_cr_read_1(chp, wd3s_qtag) != 0x55)
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{
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ct_cr_write_1(chp, wd3s_qtag, 0x0);
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goto out;
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}
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ct_cr_write_1(chp, wd3s_qtag, 0x0);
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*chiprevp = CT_WD33C93_B;
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}
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out:
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(void) ct_stat_read_1(chp);
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(void) ct_cr_read_1(chp, wd3s_stat);
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return 0;
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}
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static struct ct_synch_data *
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ct_make_synch_table(ct)
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struct ct_softc *ct;
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{
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struct ct_synch_data *sdtp, *sdp;
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u_int base, i, period;
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sdtp = sdp = &ct->sc_default_sdt[0];
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if ((ct->sc_chipclk % 5) == 0)
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base = 1000 / (5 * 2); /* 5 MHz type */
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else
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base = 1000 / (4 * 2); /* 4 MHz type */
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if (ct->sc_chiprev >= CT_WD33C93_B)
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{
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/* fast scsi */
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for (i = 2; i < 8; i ++, sdp ++)
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{
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period = (base * i) / 2;
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if (period >= 200) /* 5 MHz */
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break;
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sdp->cs_period = period / 4;
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sdp->cs_syncr = (i * 0x10) | 0x80;
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}
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}
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for (i = 2; i < 8; i ++, sdp ++)
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{
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period = (base * i);
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if (period > 500) /* 2 MHz */
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break;
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sdp->cs_period = period / 4;
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sdp->cs_syncr = (i * 0x10);
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}
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sdp->cs_period = 0;
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sdp->cs_syncr = 0;
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return sdtp;
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}
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/**************************************************
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* Attach & Probe
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**************************************************/
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int
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ctprobesubr(chp, dvcfg, hsid, chipclk, chiprevp)
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struct ct_bus_access_handle *chp;
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u_int dvcfg, chipclk;
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int hsid;
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int *chiprevp;
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{
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#if 0
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if ((ct_stat_read_1(chp) & STR_BSY) != 0)
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return 0;
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#endif
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if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0)
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return 0;
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return 1;
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}
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int
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ctprint(aux, name)
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void *aux;
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const char *name;
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{
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if (name != NULL)
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printf("%s: scsibus ", name);
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return UNCONF;
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}
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void
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ctattachsubr(ct)
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struct ct_softc *ct;
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{
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struct scsi_low_softc *slp = &ct->sc_sclow;
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ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
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slp->sl_funcs = &ct_funcs;
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slp->sl_flags |= HW_READ_PADDING;
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(void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS,
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sizeof(struct ct_targ_info), 0);
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}
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/**************************************************
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* SCSI LOW interface functions
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**************************************************/
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static void
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cthw_attention(ct)
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struct ct_softc *ct;
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{
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struct ct_bus_access_handle *chp = &ct->sc_ch;
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ct->sc_atten = 1;
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if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0)
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return;
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ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN);
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SCSI_LOW_DELAY(10);
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if ((ct_stat_read_1(chp) & STR_LCI) == 0)
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ct->sc_atten = 0;
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ct_unbusy(ct);
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return;
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}
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static void
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ct_attention(ct)
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struct ct_softc *ct;
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{
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struct scsi_low_softc *slp = &ct->sc_sclow;
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if (slp->sl_atten == 0)
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{
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ct_unbusy(ct);
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scsi_low_attention(slp);
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}
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else if (ct->sc_atten != 0)
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{
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ct_unbusy(ct);
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cthw_attention(ct);
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}
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}
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static int
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ct_targ_init(ct, ti, action)
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struct ct_softc *ct;
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struct targ_info *ti;
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int action;
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{
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struct ct_targ_info *cti = (void *) ti;
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if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
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{
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if (ct->sc_sdp == NULL)
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{
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ct->sc_sdp = ct_make_synch_table(ct);
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}
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switch (ct->sc_chiprev)
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{
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default:
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ti->ti_maxsynch.offset = 5;
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break;
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case CT_WD33C93_A:
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case CT_AM33C93_A:
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ti->ti_maxsynch.offset = 12;
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break;
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case CT_WD33C93_B:
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case CT_WD33C93_C:
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ti->ti_maxsynch.offset = 12;
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break;
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}
|
|
|
|
ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period;
|
|
ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
|
|
cti->cti_syncreg = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ct_world_start(ct, fdone)
|
|
struct ct_softc *ct;
|
|
int fdone;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
|
|
if (ct->sc_sdp == NULL)
|
|
{
|
|
ct->sc_sdp = ct_make_synch_table(ct);
|
|
}
|
|
|
|
if (slp->sl_cfgflags & CFG_NOPARITY)
|
|
ct->sc_creg = CR_DEFAULT;
|
|
else
|
|
ct->sc_creg = CR_DEFAULT_HP;
|
|
|
|
if (ct->sc_dma & CT_DMA_DMASTART)
|
|
(*ct->ct_dma_xfer_stop) (ct);
|
|
if (ct->sc_dma & CT_DMA_PIOSTART)
|
|
(*ct->ct_pio_xfer_stop) (ct);
|
|
ct->sc_dma = 0;
|
|
ct->sc_atten = 0;
|
|
|
|
cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
|
|
scsi_low_bus_reset(slp);
|
|
cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
|
|
|
|
SOFT_INTR_REQUIRED(slp);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ct_start_selection(ct, cb)
|
|
struct ct_softc *ct;
|
|
struct slccb *cb;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
|
|
struct targ_info *ti = slp->sl_Tnexus;
|
|
struct lun_info *li = slp->sl_Lnexus;
|
|
int s, satok;
|
|
u_int8_t cmd;
|
|
|
|
ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
|
|
ct->sc_atten = 0;
|
|
satok = 0;
|
|
|
|
if (scsi_low_is_disconnect_ok(cb) != 0)
|
|
{
|
|
if (ct->sc_chiprev >= CT_WD33C93_A)
|
|
satok = 1;
|
|
else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0)
|
|
satok = 1;
|
|
}
|
|
|
|
if (satok != 0 &&
|
|
scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0)
|
|
{
|
|
cmd = WD3S_SELECT_ATN_TFR;
|
|
ct->sc_satgo = CT_SAT_GOING;
|
|
}
|
|
else
|
|
{
|
|
cmd = WD3S_SELECT_ATN;
|
|
ct->sc_satgo = 0;
|
|
}
|
|
|
|
if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0)
|
|
return SCSI_LOW_START_FAIL;
|
|
|
|
if ((ct->sc_satgo & CT_SAT_GOING) != 0)
|
|
{
|
|
(void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT);
|
|
scsi_low_cmd(slp, ti);
|
|
ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
|
|
ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
|
|
}
|
|
else
|
|
{
|
|
/* anyway attention assert */
|
|
SCSI_LOW_ASSERT_ATN(slp);
|
|
}
|
|
|
|
ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction);
|
|
|
|
s = splhigh();
|
|
if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0)
|
|
{
|
|
/* XXX:
|
|
* Reload a lun again here.
|
|
*/
|
|
ct_cr_write_1(chp, wd3s_lun, li->li_lun);
|
|
ct_cr_write_1(chp, wd3s_cmd, cmd);
|
|
if ((ct_stat_read_1(chp) & STR_LCI) == 0)
|
|
{
|
|
splx(s);
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
|
|
return SCSI_LOW_START_OK;
|
|
}
|
|
}
|
|
splx(s);
|
|
return SCSI_LOW_START_FAIL;
|
|
}
|
|
|
|
static int
|
|
ct_msg(ct, ti, msg)
|
|
struct ct_softc *ct;
|
|
struct targ_info *ti;
|
|
u_int msg;
|
|
{
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
struct ct_targ_info *cti = (void *) ti;
|
|
struct ct_synch_data *csp = ct->sc_sdp;
|
|
u_int offset, period;
|
|
int error;
|
|
|
|
if ((msg & SCSI_LOW_MSG_WIDE) != 0)
|
|
{
|
|
if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
|
|
{
|
|
ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
|
|
return EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
|
|
return 0;
|
|
|
|
offset = ti->ti_maxsynch.offset;
|
|
period = ti->ti_maxsynch.period;
|
|
for ( ; csp->cs_period != 0; csp ++)
|
|
{
|
|
if (period == csp->cs_period)
|
|
break;
|
|
}
|
|
|
|
if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0)
|
|
{
|
|
ti->ti_maxsynch.period = 0;
|
|
ti->ti_maxsynch.offset = 0;
|
|
cti->cti_syncreg = 0;
|
|
error = EINVAL;
|
|
}
|
|
else
|
|
{
|
|
cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr);
|
|
error = 0;
|
|
}
|
|
|
|
if (ct->ct_synch_setup != 0)
|
|
(*ct->ct_synch_setup) (ct, ti);
|
|
ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
|
|
return error;
|
|
}
|
|
|
|
/*************************************************
|
|
* <DATA PHASE>
|
|
*************************************************/
|
|
static int
|
|
ct_xfer(ct, data, len, direction, statp)
|
|
struct ct_softc *ct;
|
|
u_int8_t *data;
|
|
int len, direction;
|
|
u_int *statp;
|
|
{
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
int wc;
|
|
register u_int8_t aux;
|
|
|
|
*statp = 0;
|
|
if (len == 1)
|
|
{
|
|
ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
|
|
}
|
|
else
|
|
{
|
|
cthw_set_count(chp, len);
|
|
ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
|
|
}
|
|
|
|
aux = ct_stat_read_1(chp);
|
|
if ((aux & STR_LCI) != 0)
|
|
{
|
|
cthw_set_count(chp, 0);
|
|
return len;
|
|
}
|
|
|
|
for (wc = 0; wc < ct->sc_tmaxcnt; wc ++)
|
|
{
|
|
/* check data ready */
|
|
if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR))
|
|
{
|
|
if (direction == SCSI_LOW_READ)
|
|
{
|
|
*data = ct_cr_read_1(chp, wd3s_data);
|
|
if ((aux & STR_PE) != 0)
|
|
*statp |= SCSI_LOW_DATA_PE;
|
|
}
|
|
else
|
|
{
|
|
ct_cr_write_1(chp, wd3s_data, *data);
|
|
}
|
|
len --;
|
|
if (len <= 0)
|
|
break;
|
|
data ++;
|
|
}
|
|
else
|
|
{
|
|
SCSI_LOW_DELAY(1);
|
|
}
|
|
|
|
/* check phase miss */
|
|
aux = ct_stat_read_1(chp);
|
|
if ((aux & STR_INT) != 0)
|
|
break;
|
|
}
|
|
return len;
|
|
}
|
|
|
|
#define CT_PADDING_BUF_SIZE 32
|
|
|
|
static void
|
|
ct_io_xfer(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
struct sc_p *sp = &slp->sl_scp;
|
|
u_int stat;
|
|
int len;
|
|
u_int8_t pbuf[CT_PADDING_BUF_SIZE];
|
|
|
|
/* polling mode */
|
|
ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg);
|
|
|
|
if (sp->scp_datalen <= 0)
|
|
{
|
|
slp->sl_error |= PDMAERR;
|
|
|
|
if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
|
|
SCSI_LOW_BZERO(pbuf, CT_PADDING_BUF_SIZE);
|
|
ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE,
|
|
sp->scp_direction, &stat);
|
|
}
|
|
else
|
|
{
|
|
len = ct_xfer(ct, sp->scp_data, sp->scp_datalen,
|
|
sp->scp_direction, &stat);
|
|
sp->scp_data += (sp->scp_datalen - len);
|
|
sp->scp_datalen = len;
|
|
}
|
|
}
|
|
|
|
/**************************************************
|
|
* <PHASE ERROR>
|
|
**************************************************/
|
|
struct ct_err {
|
|
u_char *pe_msg;
|
|
u_int pe_err;
|
|
u_int pe_errmsg;
|
|
int pe_done;
|
|
};
|
|
|
|
struct ct_err ct_cmderr[] = {
|
|
/*0*/ { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1},
|
|
/*1*/ { "unexpected bus free", FATALIO, 0, 1},
|
|
/*2*/ { NULL, SELTIMEOUTIO, 0, 1},
|
|
/*3*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
|
|
/*4*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
|
|
/*5*/ { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1},
|
|
/*6*/ { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0},
|
|
/*7*/ { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
|
|
};
|
|
|
|
static void
|
|
ct_phase_error(ct, scsi_status)
|
|
struct ct_softc *ct;
|
|
u_int8_t scsi_status;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct targ_info *ti = slp->sl_Tnexus;
|
|
struct ct_err *pep;
|
|
u_int msg = 0;
|
|
|
|
if ((scsi_status & BSR_CM) == BSR_CMDERR &&
|
|
(scsi_status & BSR_PHVALID) == 0)
|
|
{
|
|
pep = &ct_cmderr[scsi_status & BSR_PM];
|
|
slp->sl_error |= pep->pe_err;
|
|
if ((pep->pe_err & PARITYERR) != 0)
|
|
{
|
|
if (ti->ti_phase == PH_MSGIN)
|
|
msg = SCSI_LOW_MSG_PARITY;
|
|
else
|
|
msg = SCSI_LOW_MSG_ERROR;
|
|
}
|
|
else
|
|
msg = pep->pe_errmsg;
|
|
|
|
if (msg != 0)
|
|
scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1);
|
|
|
|
if (pep->pe_msg != NULL)
|
|
{
|
|
printf("%s: phase error: %s",
|
|
slp->sl_xname, pep->pe_msg);
|
|
scsi_low_print(slp, slp->sl_Tnexus);
|
|
}
|
|
|
|
if (pep->pe_done != 0)
|
|
scsi_low_disconnected(slp, ti);
|
|
}
|
|
else
|
|
{
|
|
slp->sl_error |= FATALIO;
|
|
scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error");
|
|
}
|
|
}
|
|
|
|
/**************************************************
|
|
* ### SCSI PHASE SEQUENCER ###
|
|
**************************************************/
|
|
static int
|
|
ct_reselected(ct, scsi_status)
|
|
struct ct_softc *ct;
|
|
u_int8_t scsi_status;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
struct targ_info *ti;
|
|
u_int sid;
|
|
u_int8_t regv;
|
|
|
|
ct->sc_atten = 0;
|
|
ct->sc_satgo &= ~CT_SAT_GOING;
|
|
regv = ct_cr_read_1(chp, wd3s_sid);
|
|
if ((regv & SIDR_VALID) == 0)
|
|
return EJUSTRETURN;
|
|
|
|
sid = regv & SIDR_IDM;
|
|
if ((ti = scsi_low_reselected(slp, sid)) == NULL)
|
|
return EJUSTRETURN;
|
|
|
|
ct_target_nexus_establish(ct, 0, SCSI_LOW_READ);
|
|
if (scsi_status != BSR_AFM_RESEL)
|
|
return EJUSTRETURN;
|
|
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
|
|
regv = ct_cr_read_1(chp, wd3s_data);
|
|
if (scsi_low_msgin(slp, ti, (u_int) regv) == 0)
|
|
{
|
|
if (scsi_low_is_msgout_continue(ti, 0) != 0)
|
|
{
|
|
/* XXX: scsi_low_attetion */
|
|
scsi_low_attention(slp);
|
|
}
|
|
}
|
|
|
|
if (ct->sc_atten != 0)
|
|
{
|
|
ct_attention(ct);
|
|
}
|
|
|
|
ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
|
|
return EJUSTRETURN;
|
|
}
|
|
|
|
static int
|
|
ct_target_nexus_establish(ct, lun, dir)
|
|
struct ct_softc *ct;
|
|
int lun, dir;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
struct targ_info *ti = slp->sl_Tnexus;
|
|
struct ct_targ_info *cti = (void *) ti;
|
|
|
|
if (dir == SCSI_LOW_WRITE)
|
|
ct_cr_write_1(chp, wd3s_did, ti->ti_id);
|
|
else
|
|
ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
|
|
ct_cr_write_1(chp, wd3s_lun, lun);
|
|
ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
|
|
ct_cr_write_1(chp, wd3s_cph, 0);
|
|
ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
|
|
cthw_set_count(chp, 0);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ct_lun_nexus_establish(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
struct lun_info *li = slp->sl_Lnexus;
|
|
|
|
ct_cr_write_1(chp, wd3s_lun, li->li_lun);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ct_ccb_nexus_establish(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
struct lun_info *li = slp->sl_Lnexus;
|
|
struct targ_info *ti = slp->sl_Tnexus;
|
|
struct ct_targ_info *cti = (void *) ti;
|
|
struct slccb *cb = slp->sl_Qnexus;
|
|
|
|
ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
|
|
|
|
if ((ct->sc_satgo & CT_SAT_GOING) != 0)
|
|
{
|
|
ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
|
|
ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
|
|
}
|
|
if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
|
|
ct_cr_write_1(chp, wd3s_did, ti->ti_id);
|
|
else
|
|
ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
|
|
ct_cr_write_1(chp, wd3s_lun, li->li_lun);
|
|
ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ct_unbusy(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
int wc;
|
|
register u_int8_t regv;
|
|
|
|
for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
|
|
{
|
|
regv = ct_stat_read_1(chp);
|
|
if ((regv & (STR_BSY | STR_CIP)) == 0)
|
|
return 0;
|
|
if (regv == (u_int8_t) -1)
|
|
return EIO;
|
|
|
|
SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
|
|
}
|
|
|
|
printf("%s: unbusy timeout\n", slp->sl_xname);
|
|
return EBUSY;
|
|
}
|
|
|
|
static int
|
|
ct_catch_intr(ct)
|
|
struct ct_softc *ct;
|
|
{
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
int wc;
|
|
register u_int8_t regv;
|
|
|
|
for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
|
|
{
|
|
regv = ct_stat_read_1(chp);
|
|
if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT)
|
|
return 0;
|
|
|
|
SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
|
|
}
|
|
return EJUSTRETURN;
|
|
}
|
|
|
|
int
|
|
ctintr(arg)
|
|
void *arg;
|
|
{
|
|
struct ct_softc *ct = arg;
|
|
struct scsi_low_softc *slp = &ct->sc_sclow;
|
|
struct ct_bus_access_handle *chp = &ct->sc_ch;
|
|
struct targ_info *ti;
|
|
struct physio_proc *pp;
|
|
struct buf *bp;
|
|
u_int derror, flags;
|
|
int len, satgo, error;
|
|
u_int8_t scsi_status, regv;
|
|
|
|
again:
|
|
if (slp->sl_flags & HW_INACTIVE)
|
|
return 0;
|
|
|
|
/**************************************************
|
|
* Get status & bus phase
|
|
**************************************************/
|
|
if ((ct_stat_read_1(chp) & STR_INT) == 0)
|
|
return 0;
|
|
|
|
scsi_status = ct_cr_read_1(chp, wd3s_stat);
|
|
if (scsi_status == ((u_int8_t) -1))
|
|
return 1;
|
|
|
|
/**************************************************
|
|
* Check reselection, or nexus
|
|
**************************************************/
|
|
if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL)
|
|
{
|
|
if (ct_reselected(ct, scsi_status) == EJUSTRETURN)
|
|
return 1;
|
|
}
|
|
|
|
if ((ti = slp->sl_Tnexus) == NULL)
|
|
return 1;
|
|
|
|
/**************************************************
|
|
* Debug section
|
|
**************************************************/
|
|
#ifdef CT_DEBUG
|
|
if (ct_debug > 0)
|
|
{
|
|
scsi_low_print(slp, NULL);
|
|
printf("%s: scsi_status 0x%x\n\n", slp->sl_xname,
|
|
(u_int) scsi_status);
|
|
#ifdef DDB
|
|
if (ct_debug > 1)
|
|
SCSI_LOW_DEBUGGER("ct");
|
|
#endif /* DDB */
|
|
}
|
|
#endif /* CT_DEBUG */
|
|
|
|
/**************************************************
|
|
* Internal scsi phase
|
|
**************************************************/
|
|
satgo = ct->sc_satgo;
|
|
ct->sc_satgo &= ~CT_SAT_GOING;
|
|
|
|
switch (ti->ti_phase)
|
|
{
|
|
case PH_SELSTART:
|
|
if ((satgo & CT_SAT_GOING) == 0)
|
|
{
|
|
if (scsi_status != BSR_SELECTED)
|
|
{
|
|
ct_phase_error(ct, scsi_status);
|
|
return 1;
|
|
}
|
|
scsi_low_arbit_win(slp);
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
|
|
return 1;
|
|
}
|
|
else
|
|
{
|
|
scsi_low_arbit_win(slp);
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */
|
|
}
|
|
break;
|
|
|
|
case PH_RESEL:
|
|
if ((scsi_status & BSR_PHVALID) == 0 ||
|
|
(scsi_status & BSR_PM) != BSR_MSGIN)
|
|
{
|
|
scsi_low_restart(slp, SCSI_LOW_RESTART_HARD,
|
|
"phase miss after reselect");
|
|
return 1;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
if (slp->sl_flags & HW_PDMASTART)
|
|
{
|
|
slp->sl_flags &= ~HW_PDMASTART;
|
|
if (ct->sc_dma & CT_DMA_DMASTART)
|
|
{
|
|
(*ct->ct_dma_xfer_stop) (ct);
|
|
ct->sc_dma &= ~CT_DMA_DMASTART;
|
|
}
|
|
else if (ct->sc_dma & CT_DMA_PIOSTART)
|
|
{
|
|
(*ct->ct_pio_xfer_stop) (ct);
|
|
ct->sc_dma &= ~CT_DMA_PIOSTART;
|
|
}
|
|
else
|
|
{
|
|
scsi_low_data_finish(slp);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
/**************************************************
|
|
* parse scsi phase
|
|
**************************************************/
|
|
if (scsi_status & BSR_PHVALID)
|
|
{
|
|
/**************************************************
|
|
* Normal SCSI phase.
|
|
**************************************************/
|
|
if ((scsi_status & BSR_CM) == BSR_CMDABT)
|
|
{
|
|
ct_phase_error(ct, scsi_status);
|
|
return 1;
|
|
}
|
|
|
|
switch (scsi_status & BSR_PM)
|
|
{
|
|
case BSR_DATAOUT:
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
|
|
if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
|
|
{
|
|
ct_attention(ct);
|
|
}
|
|
goto common_data_phase;
|
|
|
|
case BSR_DATAIN:
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
|
|
if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
|
|
{
|
|
ct_attention(ct);
|
|
}
|
|
|
|
common_data_phase:
|
|
if (slp->sl_scp.scp_datalen > 0)
|
|
{
|
|
slp->sl_flags |= HW_PDMASTART;
|
|
if ((ct->sc_xmode & CT_XMODE_PIO) != 0)
|
|
{
|
|
pp = physio_proc_enter(bp);
|
|
error = (*ct->ct_pio_xfer_start) (ct);
|
|
physio_proc_leave(pp);
|
|
if (error == 0)
|
|
{
|
|
ct->sc_dma |= CT_DMA_PIOSTART;
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
if ((ct->sc_xmode & CT_XMODE_DMA) != 0)
|
|
{
|
|
error = (*ct->ct_dma_xfer_start) (ct);
|
|
if (error == 0)
|
|
{
|
|
ct->sc_dma |= CT_DMA_DMASTART;
|
|
return 1;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
|
|
{
|
|
if (!(slp->sl_flags & HW_READ_PADDING))
|
|
{
|
|
printf("%s: read padding required\n", slp->sl_xname);
|
|
return 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (!(slp->sl_flags & HW_WRITE_PADDING))
|
|
{
|
|
printf("%s: write padding required\n", slp->sl_xname);
|
|
return 1;
|
|
}
|
|
}
|
|
slp->sl_flags |= HW_PDMASTART;
|
|
}
|
|
|
|
ct_io_xfer(ct);
|
|
return 1;
|
|
|
|
case BSR_CMDOUT:
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
|
|
if (scsi_low_cmd(slp, ti) != 0)
|
|
{
|
|
ct_attention(ct);
|
|
}
|
|
|
|
if (ct_xfer(ct, slp->sl_scp.scp_cmd,
|
|
slp->sl_scp.scp_cmdlen,
|
|
SCSI_LOW_WRITE, &derror) != 0)
|
|
{
|
|
printf("%s: scsi cmd xfer short\n",
|
|
slp->sl_xname);
|
|
}
|
|
return 1;
|
|
|
|
case BSR_STATIN:
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
|
|
if ((ct_io_control & CT_USE_CCSEQ) != 0)
|
|
{
|
|
if (scsi_low_is_msgout_continue(ti, 0) != 0 ||
|
|
ct->sc_atten != 0)
|
|
{
|
|
ct_xfer(ct, ®v, 1, SCSI_LOW_READ,
|
|
&derror);
|
|
scsi_low_statusin(slp, ti,
|
|
regv | derror);
|
|
}
|
|
else
|
|
{
|
|
ct->sc_satgo |= CT_SAT_GOING;
|
|
cthw_set_count(chp, 0);
|
|
cthw_phase_bypass(ct, 0x41);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
|
|
scsi_low_statusin(slp, ti, regv | derror);
|
|
}
|
|
return 1;
|
|
|
|
case BSR_UNSPINFO0:
|
|
case BSR_UNSPINFO1:
|
|
printf("%s: illegal bus phase (0x%x)\n", slp->sl_xname,
|
|
(u_int) scsi_status);
|
|
scsi_low_print(slp, ti);
|
|
return 1;
|
|
|
|
case BSR_MSGOUT:
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
|
|
flags = SCSI_LOW_MSGOUT_UNIFY;
|
|
if (ti->ti_ophase != ti->ti_phase)
|
|
flags |= SCSI_LOW_MSGOUT_INIT;
|
|
len = scsi_low_msgout(slp, ti, flags);
|
|
|
|
if (len > 1 && slp->sl_atten == 0)
|
|
{
|
|
ct_attention(ct);
|
|
}
|
|
|
|
if (ct_xfer(ct, ti->ti_msgoutstr, len,
|
|
SCSI_LOW_WRITE, &derror) != 0)
|
|
{
|
|
printf("%s: scsi msgout xfer short\n",
|
|
slp->sl_xname);
|
|
}
|
|
SCSI_LOW_DEASSERT_ATN(slp);
|
|
ct->sc_atten = 0;
|
|
return 1;
|
|
|
|
case BSR_MSGIN:/* msg in */
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
|
|
|
|
ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
|
|
if (scsi_low_msgin(slp, ti, regv | derror) == 0)
|
|
{
|
|
if (scsi_low_is_msgout_continue(ti, 0) != 0)
|
|
{
|
|
/* XXX: scsi_low_attetion */
|
|
scsi_low_attention(slp);
|
|
}
|
|
}
|
|
|
|
if ((ct_io_control & CT_FAST_INTR) != 0)
|
|
{
|
|
if (ct_catch_intr(ct) == 0)
|
|
goto again;
|
|
}
|
|
return 1;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/**************************************************
|
|
* Special SCSI phase
|
|
**************************************************/
|
|
switch (scsi_status)
|
|
{
|
|
case BSR_SATSDP: /* SAT with save data pointer */
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
|
|
ct->sc_satgo |= CT_SAT_GOING;
|
|
scsi_low_msgin(slp, ti, MSG_SAVESP);
|
|
cthw_phase_bypass(ct, 0x41);
|
|
return 1;
|
|
|
|
case BSR_SATFIN: /* SAT COMPLETE */
|
|
/*
|
|
* emulate statusin => msgin
|
|
*/
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
|
|
scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun));
|
|
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
|
|
scsi_low_msgin(slp, ti, MSG_COMP);
|
|
|
|
scsi_low_disconnected(slp, ti);
|
|
return 1;
|
|
|
|
case BSR_ACKREQ: /* negate ACK */
|
|
if (ct->sc_atten != 0)
|
|
{
|
|
ct_attention(ct);
|
|
}
|
|
|
|
ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
|
|
if ((ct_io_control & CT_FAST_INTR) != 0)
|
|
{
|
|
/* XXX:
|
|
* Should clear a pending interrupt and
|
|
* sync with a next interrupt!
|
|
*/
|
|
ct_catch_intr(ct);
|
|
}
|
|
return 1;
|
|
|
|
case BSR_DISC: /* disconnect */
|
|
if (slp->sl_msgphase == MSGPH_NULL &&
|
|
(satgo & CT_SAT_GOING) != 0)
|
|
{
|
|
/*
|
|
* emulate disconnect msg
|
|
*/
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
|
|
scsi_low_msgin(slp, ti, MSG_DISCON);
|
|
}
|
|
scsi_low_disconnected(slp, ti);
|
|
return 1;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
ct_phase_error(ct, scsi_status);
|
|
return 1;
|
|
}
|