fa790ea99f
David Somayajulu (davidcs): Overall RDMA Driver infrastructure and iWARP Anand Khoje (akhoje@marvell.com): RoCEv1 verbs implementation MFC after:5 days
113 lines
2.9 KiB
C
113 lines
2.9 KiB
C
/*
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* Copyright (c) 2018-2019 Cavium, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __QLNXR_USER_H__
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#define __QLNXR_USER_H__
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#define QLNXR_ABI_VERSION (7)
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#define QLNXR_BE_ROCE_ABI_VERSION (1)
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/* user kernel communication data structures. */
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struct qlnxr_alloc_ucontext_resp {
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u64 db_pa;
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u32 db_size;
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uint32_t max_send_wr;
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uint32_t max_recv_wr;
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uint32_t max_srq_wr;
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uint32_t sges_per_send_wr;
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uint32_t sges_per_recv_wr;
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uint32_t sges_per_srq_wr;
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int max_cqes;
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uint8_t dpm_enabled;
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uint8_t wids_enabled;
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uint16_t wid_count;
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};
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struct qlnxr_alloc_pd_ureq {
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u64 rsvd1;
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};
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struct qlnxr_alloc_pd_uresp {
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u32 pd_id;
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};
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struct qlnxr_create_cq_ureq {
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uint64_t addr; /* user space virtual address of CQ buffer */
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size_t len; /* size of CQ buffer */
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};
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struct qlnxr_create_cq_uresp {
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u32 db_offset;
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u16 icid;
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};
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struct qlnxr_create_qp_ureq {
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u32 qp_handle_hi;
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u32 qp_handle_lo;
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/* SQ */
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uint64_t sq_addr; /* user space virtual address of SQ buffer */
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size_t sq_len; /* length of SQ buffer */
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/* RQ */
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uint64_t rq_addr; /* user space virtual address of RQ buffer */
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size_t rq_len; /* length of RQ buffer */
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};
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struct qlnxr_create_qp_uresp {
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u32 qp_id;
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int atomic_supported;
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/* SQ*/
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u32 sq_db_offset;
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u16 sq_icid;
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/* RQ */
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u32 rq_db_offset;
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u16 rq_icid;
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u32 rq_db2_offset;
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};
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struct qlnxr_create_srq_ureq {
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/* user space virtual address of producer pair */
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uint64_t prod_pair_addr;
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uint64_t srq_addr; /* user space virtual address of SQ buffer */
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size_t srq_len; /* length of SQ buffer */
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};
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struct qlnxr_create_srq_uresp {
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u16 srq_id;
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};
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#endif /* #ifndef __QLNXR_USER_H__ */
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