50 lines
2.1 KiB
C
50 lines
2.1 KiB
C
/*-
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* Copyright (c) 2013 Anish Gupta (akgupt3@gmail.com)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#ifndef _SVM_MSR_H_
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#define _SVM_MSR_H_
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/*
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* SVM CPUID function, address 0x8000_000A edx bit decoding.
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*/
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#define AMD_CPUID_SVM_NP BIT(0) /* Nested paging or RVI */
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#define AMD_CPUID_SVM_LBR BIT(1) /* Last branch virtualization */
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#define AMD_CPUID_SVM_SVML BIT(2) /* SVM lock */
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#define AMD_CPUID_SVM_NRIP_SAVE BIT(3) /* Next RIP is saved */
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#define AMD_CPUID_SVM_TSC_RATE BIT(4) /* TSC rate control. */
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#define AMD_CPUID_SVM_VMCB_CLEAN BIT(5) /* VMCB state caching */
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#define AMD_CPUID_SVM_ASID_FLUSH BIT(6) /* Flush by ASID */
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#define AMD_CPUID_SVM_DECODE_ASSIST BIT(7) /* Decode assist */
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#define AMD_CPUID_SVM_PAUSE_INC BIT(10) /* Pause intercept filter. */
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#define AMD_CPUID_SVM_PAUSE_FTH BIT(12) /* Pause filter threshold */
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#endif /* _SVM_MSR_H_ */
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