574 lines
17 KiB
C
574 lines
17 KiB
C
/*-
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* Copyright (c) 2010 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under sponsorship from
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* the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ktr.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/malloc.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/pci/pcireg.h>
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#include <machine/fdt.h>
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#include "ofw_bus_if.h"
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#include "pcib_if.h"
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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#else
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#define debugf(fmt, args...)
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#endif
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#define FDT_RANGES_CELLS ((3 + 3 + 2) * 2)
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static void
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fdt_pci_range_dump(struct fdt_pci_range *range)
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{
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#ifdef DEBUG
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printf("\n");
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printf(" base_pci = 0x%08lx\n", range->base_pci);
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printf(" base_par = 0x%08lx\n", range->base_parent);
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printf(" len = 0x%08lx\n", range->len);
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#endif
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}
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int
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fdt_pci_ranges_decode(phandle_t node, struct fdt_pci_range *io_space,
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struct fdt_pci_range *mem_space)
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{
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pcell_t ranges[FDT_RANGES_CELLS];
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struct fdt_pci_range *pci_space;
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pcell_t addr_cells, size_cells, par_addr_cells;
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pcell_t *rangesptr;
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pcell_t cell0, cell1, cell2;
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int tuple_size, tuples, i, rv, offset_cells, len;
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/*
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* Retrieve 'ranges' property.
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*/
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if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
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return (EINVAL);
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if (addr_cells != 3 || size_cells != 2)
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return (ERANGE);
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par_addr_cells = fdt_parent_addr_cells(node);
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if (par_addr_cells > 3)
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return (ERANGE);
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len = OF_getproplen(node, "ranges");
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if (len > sizeof(ranges))
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return (ENOMEM);
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if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
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return (EINVAL);
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tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
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size_cells);
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tuples = len / tuple_size;
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/*
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* Initialize the ranges so that we don't have to worry about
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* having them all defined in the FDT. In particular, it is
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* perfectly fine not to want I/O space on PCI busses.
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*/
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bzero(io_space, sizeof(*io_space));
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bzero(mem_space, sizeof(*mem_space));
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rangesptr = &ranges[0];
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offset_cells = 0;
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for (i = 0; i < tuples; i++) {
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cell0 = fdt_data_get((void *)rangesptr, 1);
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rangesptr++;
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cell1 = fdt_data_get((void *)rangesptr, 1);
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rangesptr++;
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cell2 = fdt_data_get((void *)rangesptr, 1);
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rangesptr++;
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if (cell0 & 0x02000000) {
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pci_space = mem_space;
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} else if (cell0 & 0x01000000) {
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pci_space = io_space;
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} else {
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rv = ERANGE;
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goto out;
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}
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if (par_addr_cells == 3) {
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/*
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* This is a PCI subnode 'ranges'. Skip cell0 and
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* cell1 of this entry and only use cell2.
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*/
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offset_cells = 2;
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rangesptr += offset_cells;
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}
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if (fdt_data_verify((void *)rangesptr, par_addr_cells -
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offset_cells)) {
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rv = ERANGE;
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goto out;
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}
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pci_space->base_parent = fdt_data_get((void *)rangesptr,
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par_addr_cells - offset_cells);
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rangesptr += par_addr_cells - offset_cells;
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if (fdt_data_verify((void *)rangesptr, size_cells)) {
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rv = ERANGE;
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goto out;
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}
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pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
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rangesptr += size_cells;
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pci_space->base_pci = cell2;
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}
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rv = 0;
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out:
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return (rv);
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}
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int
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fdt_pci_ranges(phandle_t node, struct fdt_pci_range *io_space,
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struct fdt_pci_range *mem_space)
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{
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int err;
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debugf("Processing PCI node: %x\n", node);
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if ((err = fdt_pci_ranges_decode(node, io_space, mem_space)) != 0) {
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debugf("could not decode parent PCI node 'ranges'\n");
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return (err);
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}
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debugf("Post fixup dump:\n");
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fdt_pci_range_dump(io_space);
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fdt_pci_range_dump(mem_space);
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return (0);
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}
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static int
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fdt_addr_cells(phandle_t node, int *addr_cells)
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{
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pcell_t cell;
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int cell_size;
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cell_size = sizeof(cell);
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if (OF_getprop(node, "#address-cells", &cell, cell_size) < cell_size)
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return (EINVAL);
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*addr_cells = fdt32_to_cpu((int)cell);
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if (*addr_cells > 3)
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return (ERANGE);
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return (0);
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}
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static int
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fdt_interrupt_cells(phandle_t node)
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{
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pcell_t intr_cells;
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if (OF_getprop(node, "#interrupt-cells", &intr_cells,
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sizeof(intr_cells)) <= 0) {
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debugf("no intr-cells defined, defaulting to 1\n");
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intr_cells = 1;
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}
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intr_cells = fdt32_to_cpu(intr_cells);
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return ((int)intr_cells);
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}
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int
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fdt_pci_intr_info(phandle_t node, struct fdt_pci_intr *intr_info)
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{
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void *map, *mask;
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int acells, icells;
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int error, len;
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error = fdt_addr_cells(node, &acells);
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if (error)
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return (error);
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icells = fdt_interrupt_cells(node);
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/*
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* Retrieve the interrupt map and mask properties.
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*/
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len = OF_getprop_alloc(node, "interrupt-map-mask", 1, &mask);
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if (len / sizeof(pcell_t) != (acells + icells)) {
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debugf("bad mask len = %d\n", len);
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goto err;
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}
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len = OF_getprop_alloc(node, "interrupt-map", 1, &map);
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if (len <= 0) {
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debugf("bad map len = %d\n", len);
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goto err;
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}
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intr_info->map_len = len;
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intr_info->map = map;
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intr_info->mask = mask;
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intr_info->addr_cells = acells;
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intr_info->intr_cells = icells;
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debugf("acells=%u, icells=%u, map_len=%u\n", acells, icells, len);
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return (0);
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err:
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free(mask, M_OFWPROP);
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return (ENXIO);
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}
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int
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fdt_pci_route_intr(int bus, int slot, int func, int pin,
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struct fdt_pci_intr *intr_info, int *interrupt)
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{
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pcell_t child_spec[4], masked[4];
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ihandle_t iph;
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pcell_t intr_par;
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pcell_t *map_ptr;
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uint32_t addr;
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int i, j, map_len;
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int par_intr_cells, par_addr_cells, child_spec_cells, row_cells;
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int par_idx, spec_idx, err, trig, pol;
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child_spec_cells = intr_info->addr_cells + intr_info->intr_cells;
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if (child_spec_cells > sizeof(child_spec) / sizeof(pcell_t))
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return (ENOMEM);
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addr = (bus << 16) | (slot << 11) | (func << 8);
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child_spec[0] = addr;
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child_spec[1] = 0;
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child_spec[2] = 0;
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child_spec[3] = pin;
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map_len = intr_info->map_len;
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map_ptr = intr_info->map;
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par_idx = child_spec_cells;
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i = 0;
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while (i < map_len) {
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iph = fdt32_to_cpu(map_ptr[par_idx]);
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intr_par = OF_instance_to_package(iph);
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err = fdt_addr_cells(intr_par, &par_addr_cells);
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if (err != 0) {
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debugf("could not retrieve intr parent #addr-cells\n");
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return (err);
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}
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par_intr_cells = fdt_interrupt_cells(intr_par);
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row_cells = child_spec_cells + 1 + par_addr_cells +
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par_intr_cells;
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/*
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* Apply mask and look up the entry in interrupt map.
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*/
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for (j = 0; j < child_spec_cells; j++) {
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masked[j] = child_spec[j] &
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fdt32_to_cpu(intr_info->mask[j]);
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if (masked[j] != fdt32_to_cpu(map_ptr[j]))
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goto next;
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}
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/*
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* Decode interrupt of the parent intr controller.
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*/
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spec_idx = child_spec_cells + 1 + par_addr_cells;
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err = fdt_intr_decode(intr_par, &map_ptr[spec_idx],
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interrupt, &trig, &pol);
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if (err != 0) {
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debugf("could not decode interrupt\n");
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return (err);
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}
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debugf("decoded intr = %d, trig = %d, pol = %d\n", *interrupt,
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trig, pol);
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#if defined(__powerpc__)
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powerpc_config_intr(FDT_MAP_IRQ(intr_par, *interrupt), trig,
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pol);
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#endif
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return (0);
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next:
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map_ptr += row_cells;
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i += (row_cells * sizeof(pcell_t));
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}
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return (ENXIO);
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}
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#if defined(__arm__)
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int
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fdt_pci_devmap(phandle_t node, struct pmap_devmap *devmap, vm_offset_t io_va,
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vm_offset_t mem_va)
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{
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struct fdt_pci_range io_space, mem_space;
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int error;
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if ((error = fdt_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
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return (error);
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devmap->pd_va = (io_va ? io_va : io_space.base_parent);
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devmap->pd_pa = io_space.base_parent;
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devmap->pd_size = io_space.len;
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devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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devmap->pd_cache = PTE_NOCACHE;
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devmap++;
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devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
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devmap->pd_pa = mem_space.base_parent;
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devmap->pd_size = mem_space.len;
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devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
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devmap->pd_cache = PTE_NOCACHE;
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return (0);
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}
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#endif
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#if 0
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static int
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fdt_pci_config_bar(device_t dev, int bus, int slot, int func, int bar)
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{
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}
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static int
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fdt_pci_config_normal(device_t dev, int bus, int slot, int func)
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{
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int bar;
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uint8_t command, intline, intpin;
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command = PCIB_READ_CONFIG(dev, bus, slot, func, PCIR_COMMAND, 1);
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command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
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PCIB_WRITE_CONFIG(dev, bus, slot, func, PCIR_COMMAND, command, 1);
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/* Program the base address registers. */
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bar = 0;
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while (bar <= PCIR_MAX_BAR_0)
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bar += fdt_pci_config_bar(dev, bus, slot, func, bar);
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/* Perform interrupt routing. */
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intpin = PCIB_READ_CONFIG(dev, bus, slot, func, PCIR_INTPIN, 1);
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intline = fsl_pcib_route_int(dev, bus, slot, func, intpin);
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PCIB_WRITE_CONFIG(dev, bus, slot, func, PCIR_INTLINE, intline, 1);
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command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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PCIB_WRITE_CONFIG(dev, bus, slot, func, PCIR_COMMAND, command, 1);
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}
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static int
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fdt_pci_config_bridge(device_t dev, int bus, int secbus, int slot, int func)
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{
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int maxbar;
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uint8_t command;
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command = PCIB_READ_CONFIG(dev, bus, slot, func, PCIR_COMMAND, 1);
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command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
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PCIB_WRITE_CONFIG(dev, bus, slot, func, PCIR_COMMAND, command, 1);
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/* Program the base address registers. */
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maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6;
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bar = 0;
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while (bar < maxbar)
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bar += fsl_pcib_init_bar(sc, bus, slot, func,
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bar);
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/* Perform interrupt routing. */
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intpin = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_INTPIN, 1);
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intline = fsl_pcib_route_int(sc, bus, slot, func,
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intpin);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_INTLINE, intline, 1);
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command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_COMMAND, command, 1);
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/*
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* Handle PCI-PCI bridges
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*/
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class = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_CLASS, 1);
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subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot,
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func, PCIR_SUBCLASS, 1);
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/* Allow only proper PCI-PCI briges */
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if (class != PCIC_BRIDGE)
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continue;
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if (subclass != PCIS_BRIDGE_PCI)
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continue;
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secbus++;
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/* Program I/O decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2);
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/* Program (non-prefetchable) memory decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2);
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/* Program prefetchable memory decoder. */
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMBASEL_1, 0x0010, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMLIMITL_1, 0x000f, 2);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMBASEH_1, 0x00000000, 4);
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fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
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PCIR_PMLIMITH_1, 0x00000000, 4);
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/* Read currect bus register configuration */
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old_pribus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_PRIBUS_1, 1);
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old_secbus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_SECBUS_1, 1);
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old_subbus = fsl_pcib_read_config(sc->sc_dev, bus,
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slot, func, PCIR_SUBBUS_1, 1);
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if (bootverbose)
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printf("PCI: reading firmware bus numbers for "
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"secbus = %d (bus/sec/sub) = (%d/%d/%d)\n",
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secbus, old_pribus, old_secbus, old_subbus);
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new_pribus = bus;
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new_secbus = secbus;
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secbus = fsl_pcib_init(sc, secbus,
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(subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0);
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new_subbus = secbus;
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if (bootverbose)
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printf("PCI: translate firmware bus numbers "
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"for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n",
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secbus, old_pribus, old_secbus, old_subbus,
|
|
new_pribus, new_secbus, new_subbus);
|
|
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_PRIBUS_1, new_pribus, 1);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_SECBUS_1, new_secbus, 1);
|
|
fsl_pcib_write_config(sc->sc_dev, bus, slot, func,
|
|
PCIR_SUBBUS_1, new_subbus, 1);
|
|
|
|
}
|
|
|
|
static int
|
|
fdt_pci_config_slot(device_t dev, int bus, int secbus, int slot)
|
|
{
|
|
int func, maxfunc;
|
|
uint16_t vendor;
|
|
uint8_t hdrtype;
|
|
|
|
maxfunc = 0;
|
|
for (func = 0; func <= maxfunc; func++) {
|
|
hdrtype = PCIB_READ_CONFIG(dev, bus, slot, func,
|
|
PCIR_HDRTYPE, 1);
|
|
if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
|
|
continue;
|
|
if (func == 0 && (hdrtype & PCIM_MFDEV))
|
|
maxfunc = PCI_FUNCMAX;
|
|
|
|
vendor = PCIB_READ_CONFIG(dev, bus, slot, func,
|
|
PCIR_VENDOR, 2);
|
|
if (vendor == 0xffff)
|
|
continue;
|
|
|
|
if ((hdrtype & PCIM_HDRTYPE) == PCIM_HDRTYPE_NORMAL)
|
|
fdt_pci_config_normal(dev, bus, slot, func);
|
|
else
|
|
secbus = fdt_pci_config_bridge(dev, bus, secbus,
|
|
slot, func);
|
|
}
|
|
|
|
return (secbus);
|
|
}
|
|
|
|
static int
|
|
fdt_pci_config_bus(device_t dev, int bus, int maxslot)
|
|
{
|
|
int func, maxfunc, secbus, slot;
|
|
|
|
secbus = bus;
|
|
for (slot = 0; slot <= maxslot; slot++)
|
|
secbus = fdt_pci_config_slot(dev, bus, secbus, slot);
|
|
|
|
return (secbus);
|
|
}
|
|
|
|
int
|
|
fdt_pci_config_domain(device_t dev)
|
|
{
|
|
pcell_t bus_range[2];
|
|
phandle_t root;
|
|
int bus, error, maxslot;
|
|
|
|
root = ofw_bus_get_node(dev);
|
|
if (root == 0)
|
|
return (EINVAL);
|
|
if (!fdt_is_type(root, "pci"))
|
|
return (EINVAL);
|
|
|
|
/*
|
|
* Determine the bus number of the root in this domain.
|
|
* Lacking any information, this will be bus 0.
|
|
* Write the bus number to the bus device, using the IVAR.
|
|
*/
|
|
if ((OF_getprop(root, "bus-range", bus_range, sizeof(bus_range)) <= 0)
|
|
bus = 0;
|
|
else
|
|
bus = fdt32_to_cpu(bus_range[0]);
|
|
|
|
error = BUS_WRITE_IVAR(dev, NULL, PCIB_IVAR_BUS, bus);
|
|
if (error)
|
|
return (error);
|
|
|
|
/* Get the maximum slot number for bus-enumeration. */
|
|
maxslot = PCIB_MAXSLOTS(dev);
|
|
|
|
bus = fdt_pci_config_bus(dev, bus, maxslot);
|
|
return (0);
|
|
}
|
|
#endif
|