b502e57d9e
OCTEON2 family of processors should live in mips/octeon2. Not enough is know abotu the former to know if the same port can be used for both yet.
144 lines
3.2 KiB
ArmAsm
144 lines
3.2 KiB
ArmAsm
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#include <machine/asm.h>
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#include <machine/cache_r4k.h>
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#include <machine/cpuregs.h>
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#include <machine/param.h>
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#include <machine/pte.h>
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#include "assym.s"
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#define CPU_DISABLE_INTERRUPTS(reg, reg2, reg3) \
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mfc0 reg, MIPS_COP_0_STATUS; \
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nop; \
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move reg3, reg; \
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li reg2, ~MIPS_SR_INT_IE; \
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and reg, reg2, reg; \
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mtc0 reg, MIPS_COP_0_STATUS; \
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COP0_SYNC
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#define CPU_ENABLE_INTERRUPTS(reg, reg3) \
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mfc0 reg, MIPS_COP_0_STATUS; \
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nop; \
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or reg, reg, reg3; \
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mtc0 reg, MIPS_COP_0_STATUS; \
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COP0_SYNC
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#define PUSHR(reg) \
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addiu sp,sp,-16 ; \
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sd reg, 8(sp) ; \
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nop ;
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#define POPR(reg) \
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ld reg, 8(sp) ; \
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addiu sp,sp,16 ; \
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nop ;
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/*
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* octeon_ciu_get_interrupt_reg_addr
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*
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* Given Int-X, En-X combination, return the CIU Interrupt Enable Register addr
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* a0 = ciu Int-X: 0/1
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* a1 = ciu EN-0: 0/1
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*/
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LEAF(octeon_ciu_get_interrupt_reg_addr)
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.set noreorder
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.set mips3
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beqz a0, ciu_get_interrupt_reg_addr_Int_0
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nop
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ciu_get_interrupt_reg_addr_Int_1:
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beqz a1, ciu_get_interrupt_reg_addr_Int_1_En_0
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nop
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ciu_get_interrupt_reg_addr_Int_1_En1:
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li a0, OCTEON_CIU_ADDR_HI
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dsll32 a0, a0, 0
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nop
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ori a0, OCTEON_CIU_EN1_INT1_LO
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j ciu_get_interrupt_reg_addr_ret
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nop
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ciu_get_interrupt_reg_addr_Int_1_En_0:
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li a0, OCTEON_CIU_ADDR_HI
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dsll32 a0, a0, 0
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nop
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ori a0, OCTEON_CIU_EN0_INT1_LO
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j ciu_get_interrupt_reg_addr_ret
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nop
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ciu_get_interrupt_reg_addr_Int_0:
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beqz a1, ciu_get_interrupt_reg_addr_Int_0_En_0
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nop
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ciu_get_interrupt_reg_addr_Int_0_En_1:
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li a0, OCTEON_CIU_ADDR_HI
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dsll32 a0, a0, 0
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nop
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ori a0, OCTEON_CIU_EN1_INT0_LO
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j ciu_get_interrupt_reg_addr_ret
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nop
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ciu_get_interrupt_reg_addr_Int_0_En_0:
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li a0, OCTEON_CIU_ADDR_HI
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dsll32 a0, a0, 0
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nop
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ori a0, OCTEON_CIU_EN0_INT0_LO
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ciu_get_interrupt_reg_addr_ret:
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j ra
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nop
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.set mips0
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.set reorder
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END(octeon_ciu_get_interrupt_reg_addr)
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/*
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* octeon_ciu_mask_all_interrupts
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*
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* a0 = ciu Interrupt-X: 0/1
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* a1 = ciu Enable-X: 0/1
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*/
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LEAF(octeon_ciu_mask_all_interrupts)
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.set noreorder
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.set mips3
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PUSHR(ra)
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PUSHR(s0)
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move t0, a0
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move t1, a1
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li a0, MIPS_SR_INT_IE
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CPU_DISABLE_INTERRUPTS(a2, a1, s0)
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move a0, t0
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move t1, a1
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jal octeon_ciu_get_interrupt_reg_addr
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nop
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ld a2, 0(a0) # Dummy read
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nop
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move a2, zero # Clear all
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sd a2, 0(a0) # Write new Enable bits
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nop
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CPU_ENABLE_INTERRUPTS(a2, s0)
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POPR(s0)
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POPR(ra)
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j ra # Return
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nop # (bd slot)
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.set mips0
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.set reorder
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END(octeon_ciu_mask_all_interrupts)
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