517904de5c
This controller supports 2.5G/1G/100MB/10MB speeds, and allows
tx/rx checksum offload, TSO, LRO, and multi-queue operation.
The driver was derived from code contributed by Intel, and modified
by Netgate to fit into the iflib framework.
Thanks to Mike Karels for testing and feedback on the driver.
Reviewed by: bcr (manpages), kbowling, scottl, erj
MFC after: 1 month
Relnotes: yes
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D30668
33 lines
1.1 KiB
C
33 lines
1.1 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* $FreeBSD$
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*/
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#ifndef _IGC_NVM_H_
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#define _IGC_NVM_H_
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void igc_init_nvm_ops_generic(struct igc_hw *hw);
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s32 igc_null_read_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);
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void igc_null_nvm_generic(struct igc_hw *hw);
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s32 igc_null_led_default(struct igc_hw *hw, u16 *data);
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s32 igc_null_write_nvm(struct igc_hw *hw, u16 a, u16 b, u16 *c);
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s32 igc_acquire_nvm_generic(struct igc_hw *hw);
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s32 igc_poll_eerd_eewr_done(struct igc_hw *hw, int ee_reg);
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s32 igc_read_mac_addr_generic(struct igc_hw *hw);
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s32 igc_read_pba_string_generic(struct igc_hw *hw, u8 *pba_num,
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u32 pba_num_size);
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s32 igc_read_nvm_eerd(struct igc_hw *hw, u16 offset, u16 words,
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u16 *data);
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s32 igc_valid_led_default_generic(struct igc_hw *hw, u16 *data);
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s32 igc_validate_nvm_checksum_generic(struct igc_hw *hw);
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s32 igc_write_nvm_spi(struct igc_hw *hw, u16 offset, u16 words,
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u16 *data);
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s32 igc_update_nvm_checksum_generic(struct igc_hw *hw);
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void igc_release_nvm_generic(struct igc_hw *hw);
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#endif
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