f5f9340b98
New kernel events can be added at various location for sampling or counting. This will for example allow easy system profiling whatever the processor is with known tools like pmcstat(8). Simultaneous usage of software PMC and hardware PMC is possible, for example looking at the lock acquire failure, page fault while sampling on instructions. Sponsored by: NETASQ MFC after: 1 month
267 lines
7.3 KiB
Groff
267 lines
7.3 KiB
Groff
.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd October 4, 2008
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.Dt PMC.K7 3
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.Os
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.Sh NAME
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.Nm pmc.k7
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.Nd measurement events for
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.Tn AMD
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.Tn Athlon
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(K7 family) CPUs
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.Sh LIBRARY
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.Lb libpmc
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.Sh SYNOPSIS
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.In pmc.h
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.Sh DESCRIPTION
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AMD K7 PMCs are present in the
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.Tn "AMD Athlon"
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series of CPUs and are documented in:
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.Rs
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.%B "AMD Athlon Processor x86 Code Optimization Guide"
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.%N "Publication No. 22007"
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.%D "February 2002"
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.%Q "Advanced Micro Devices, Inc."
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.Re
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.Ss PMC Features
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AMD K7 PMCs are 48 bits wide.
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Each K7 CPU contains 4 PMCs with the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
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.It PMC_CAP_EDGE Ta Yes
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.It PMC_CAP_INTERRUPT Ta Yes
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.It PMC_CAP_INVERT Ta Yes
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.It PMC_CAP_READ Ta Yes
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.It PMC_CAP_PRECISE Ta \&No
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.It PMC_CAP_SYSTEM Ta Yes
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.It PMC_CAP_TAGGING Ta \&No
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.It PMC_CAP_THRESHOLD Ta Yes
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.It PMC_CAP_USER Ta Yes
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.It PMC_CAP_WRITE Ta Yes
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.El
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.Ss Event Qualifiers
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Event specifiers for AMD K7 PMCs can have the following optional
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qualifiers:
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.Bl -tag -width indent
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.It Li count= Ns Ar value
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Configure the counter to increment only if the number of configured
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events measured in a cycle is greater than or equal to
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.Ar value .
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.It Li edge
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Configure the counter to only count negated-to-asserted transitions
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of the conditions expressed by the other qualifiers.
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In other words, the counter will increment only once whenever a given
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condition becomes true, irrespective of the number of clocks during
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which the condition remains true.
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.It Li inv
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Invert the sense of comparison when the
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.Dq Li count
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qualifier is present, making the counter to increment when the
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number of events per cycle is less than the value specified by
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the
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.Dq Li count
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qualifier.
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.It Li os
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Configure the PMC to count events happening at privilege level 0.
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.It Li unitmask= Ns Ar mask
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This qualifier is used to further qualify a select few events,
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.Dq Li k7-dc-refills-from-l2 ,
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.Dq Li k7-dc-refills-from-system
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and
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.Dq Li k7-dc-writebacks .
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Here
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.Ar mask
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is a string of the following characters optionally separated by
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.Ql +
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characters:
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.Pp
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.Bl -tag -width indent -compact
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.It Li m
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Count operations for lines in the
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.Dq Modified
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state.
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.It Li o
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Count operations for lines in the
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.Dq Owner
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state.
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.It Li e
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Count operations for lines in the
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.Dq Exclusive
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state.
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.It Li s
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Count operations for lines in the
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.Dq Shared
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state.
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.It Li i
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Count operations for lines in the
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.Dq Invalid
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state.
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.El
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.Pp
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If no
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.Dq Li unitmask
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qualifier is specified, the default is to count events for caches
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lines in any of the above states.
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.It Li usr
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Configure the PMC to count events occurring at privilege levels 1, 2
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or 3.
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.El
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.Pp
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If neither of the
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.Dq Li os
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or
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.Dq Li usr
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qualifiers were specified, the default is to enable both.
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.Ss AMD K7 Event Specifiers
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The event specifiers supported on AMD K7 PMCs are:
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.Bl -tag -width indent
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.It Li k7-dc-accesses
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.Pq Event 40H
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Count data cache accesses.
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.It Li k7-dc-misses
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.Pq Event 41H
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Count data cache misses.
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.It Li k7-dc-refills-from-l2 Op Li ,unitmask= Ns Ar mask
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.Pq Event 42H
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Count data cache refills from L2 cache.
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This event may be further qualified using the
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.Dq Li unitmask
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qualifier.
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.It Li k7-dc-refills-from-system Op Li ,unitmask= Ns Ar mask
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.Pq Event 43H
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Count data cache refills from system memory.
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This event may be further qualified using the
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.Dq Li unitmask
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qualifier.
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.It Li k7-dc-writebacks Op Li ,unitmask= Ns Ar mask
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.Pq Event 44H
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Count data cache writebacks.
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This event may be further qualified using the
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.Dq Li unitmask
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qualifier.
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.It Li k7-hardware-interrupts
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.Pq Event CFH
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Count the number of taken hardware interrupts.
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.It Li k7-ic-fetches
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.Pq Event 80H
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Count instruction cache fetches.
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.It Li k7-ic-misses
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.Pq Event 81H
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Count instruction cache misses.
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.It Li k7-interrupts-masked-cycles
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.Pq Event CDH
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Count the number of cycles when the processor's
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.Va IF
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flag was zero.
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.It Li k7-interrupts-masked-while-pending-cycles
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.Pq Event CEH
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Count the number of cycles interrupts were masked while pending due
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to the processor's
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.Va IF
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flag being zero.
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.It Li k7-l1-and-l2-dtlb-misses
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.Pq Event 46H
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Count L1 and L2 DTLB misses.
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.It Li k7-l1-dtlb-miss-and-l2-dtlb-hits
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.Pq Event 45H
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Count L1 DTLB misses and L2 DTLB hits.
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.It Li k7-l1-itlb-misses
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.Pq Event 84H
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Count L1 ITLB misses that are L2 ITLB hits.
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.It Li k7-l1-l2-itlb-misses
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.Pq Event 85H
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Count L1 (and L2) ITLB misses.
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.It Li k7-misaligned-references
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.Pq Event 47H
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Count misaligned data references.
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.It Li k7-retired-branches
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.Pq Event C2H
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Count all retired branches (conditional, unconditional, exceptions
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and interrupts).
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.It Li k7-retired-branches-mispredicted
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.Pq Event C3H
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Count all mispredicted retired branches.
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.It Li k7-retired-far-control-transfers
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.Pq Event C6H
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Count retired far control transfers.
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.It Li k7-retired-instructions
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.Pq Event C0H
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Count all retired instructions.
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.It Li k7-retired-ops
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.Pq Event C1H
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Count retired ops.
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.It Li k7-retired-resync-branches
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.Pq Event C7H
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Count retired resync branches (non control transfer branches).
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.It Li k7-retired-taken-branches
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.Pq Event C4H
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Count retired taken branches.
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.It Li k7-retired-taken-branches-mispredicted
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.Pq Event C5H
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Count mispredicted taken branches that were retired.
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.El
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.Ss Event Name Aliases
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The following table shows the mapping between the PMC-independent
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aliases supported by
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.Lb libpmc
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and the underlying hardware events used.
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.Bl -column "branch-mispredicts" "Description"
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.It Em Alias Ta Em Event
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.It Li branches Ta Li k7-retired-branches
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.It Li branch-mispredicts Ta Li k7-retired-branches-mispredicted
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.It Li dc-misses Ta Li k7-dc-misses
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.It Li ic-misses Ta Li k7-ic-misses
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.It Li instructions Ta Li k7-retired-instructions
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.It Li interrupts Ta Li k7-hardware-interrupts
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.It Li unhalted-cycles Ta (unsupported)
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.El
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.Sh SEE ALSO
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.Xr pmc 3 ,
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.Xr pmc.atom 3 ,
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.Xr pmc.core 3 ,
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.Xr pmc.core2 3 ,
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.Xr pmc.iaf 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmclog 3 ,
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.Xr hwpmc 4
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.Sh HISTORY
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The
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.Nm pmc
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library first appeared in
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.Fx 6.0 .
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.Sh AUTHORS
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The
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.Lb libpmc
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library was written by
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.An "Joseph Koshy"
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.Aq jkoshy@FreeBSD.org .
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