04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
231 lines
11 KiB
C
231 lines
11 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-pcm-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon pcm.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_PCM_TYPEDEFS_H__
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#define __CVMX_PCM_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_PCM_CLKX_CFG(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
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cvmx_warn("CVMX_PCM_CLKX_CFG(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384;
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}
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#else
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#define CVMX_PCM_CLKX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001070000010000ull) + ((offset) & 1) * 16384)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_PCM_CLKX_DBG(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
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cvmx_warn("CVMX_PCM_CLKX_DBG(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384;
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}
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#else
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#define CVMX_PCM_CLKX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001070000010038ull) + ((offset) & 1) * 16384)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_PCM_CLKX_GEN(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1)))))
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cvmx_warn("CVMX_PCM_CLKX_GEN(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384;
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}
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#else
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#define CVMX_PCM_CLKX_GEN(offset) (CVMX_ADD_IO_SEG(0x0001070000010008ull) + ((offset) & 1) * 16384)
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#endif
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/**
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* cvmx_pcm_clk#_cfg
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*/
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union cvmx_pcm_clkx_cfg
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{
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uint64_t u64;
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struct cvmx_pcm_clkx_cfg_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t fsyncgood : 1; /**< FSYNC status
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If 1, the last frame had a correctly positioned
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fsync pulse
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If 0, none/extra fsync pulse seen on most recent
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frame
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NOTE: this is intended for startup. the FSYNCEXTRA
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and FSYNCMISSING interrupts are intended for
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detecting loss of sync during normal operation. */
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uint64_t reserved_48_62 : 15;
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uint64_t fsyncsamp : 16; /**< Number of ECLKs from internal BCLK edge to
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sample FSYNC
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NOTE: used to sync to the start of a frame and to
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check for FSYNC errors. */
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uint64_t reserved_26_31 : 6;
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uint64_t fsynclen : 5; /**< Number of 1/2 BCLKs FSYNC is asserted for
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NOTE: only used when GEN==1 */
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uint64_t fsyncloc : 5; /**< FSYNC location, in 1/2 BCLKS before timeslot 0,
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bit 0.
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NOTE: also used to detect framing errors and
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therefore must have a correct value even if GEN==0 */
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uint64_t numslots : 10; /**< Number of 8-bit slots in a frame
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NOTE: this, along with EXTRABIT and Fbclk
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determines FSYNC frequency when GEN == 1
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NOTE: also used to detect framing errors and
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therefore must have a correct value even if GEN==0 */
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uint64_t extrabit : 1; /**< If 0, no frame bit
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If 1, add one extra bit time for frame bit
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NOTE: if GEN == 1, then FSYNC will be delayed one
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extra bit time.
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NOTE: also used to detect framing errors and
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therefore must have a correct value even if GEN==0
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NOTE: the extra bit comes from the LSB/MSB of the
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first byte of the frame in the transmit memory
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region. LSB vs MSB is determined from the setting
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of PCMn_TDM_CFG[LSBFIRST]. */
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uint64_t bitlen : 2; /**< Number of BCLKs in a bit time.
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0 : 1 BCLK
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1 : 2 BCLKs
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2 : 4 BCLKs
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3 : operation undefined */
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uint64_t bclkpol : 1; /**< If 0, BCLK rise edge is start of bit time
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If 1, BCLK fall edge is start of bit time
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NOTE: also used to detect framing errors and
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therefore must have a correct value even if GEN==0 */
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uint64_t fsyncpol : 1; /**< If 0, FSYNC idles low, asserts high
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If 1, FSYNC idles high, asserts low
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NOTE: also used to detect framing errors and
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therefore must have a correct value even if GEN==0 */
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uint64_t ena : 1; /**< If 0, Clock receiving logic is doing nothing
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1, Clock receiving logic is looking for sync */
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#else
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uint64_t ena : 1;
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uint64_t fsyncpol : 1;
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uint64_t bclkpol : 1;
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uint64_t bitlen : 2;
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uint64_t extrabit : 1;
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uint64_t numslots : 10;
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uint64_t fsyncloc : 5;
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uint64_t fsynclen : 5;
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uint64_t reserved_26_31 : 6;
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uint64_t fsyncsamp : 16;
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uint64_t reserved_48_62 : 15;
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uint64_t fsyncgood : 1;
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#endif
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} s;
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struct cvmx_pcm_clkx_cfg_s cn30xx;
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struct cvmx_pcm_clkx_cfg_s cn31xx;
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struct cvmx_pcm_clkx_cfg_s cn50xx;
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};
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typedef union cvmx_pcm_clkx_cfg cvmx_pcm_clkx_cfg_t;
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/**
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* cvmx_pcm_clk#_dbg
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*/
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union cvmx_pcm_clkx_dbg
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{
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uint64_t u64;
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struct cvmx_pcm_clkx_dbg_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t debuginfo : 64; /**< Miscellaneous debug information */
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#else
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uint64_t debuginfo : 64;
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#endif
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} s;
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struct cvmx_pcm_clkx_dbg_s cn30xx;
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struct cvmx_pcm_clkx_dbg_s cn31xx;
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struct cvmx_pcm_clkx_dbg_s cn50xx;
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};
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typedef union cvmx_pcm_clkx_dbg cvmx_pcm_clkx_dbg_t;
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/**
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* cvmx_pcm_clk#_gen
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*/
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union cvmx_pcm_clkx_gen
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{
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uint64_t u64;
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struct cvmx_pcm_clkx_gen_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t deltasamp : 16; /**< Signed number of ECLKs to move sampled BCLK edge
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NOTE: the complete number of ECLKs to move is:
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NUMSAMP + 2 + 1 + DELTASAMP
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NUMSAMP to compensate for sampling delay
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+ 2 to compensate for dual-rank synchronizer
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+ 1 for uncertainity
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+ DELTASAMP to CMA/debugging */
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uint64_t numsamp : 16; /**< Number of ECLK samples to detect BCLK change when
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receiving clock. */
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uint64_t n : 32; /**< Determines BCLK frequency when generating clock
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NOTE: Fbclk = Feclk * N / 2^32
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N = (Fbclk / Feclk) * 2^32
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NOTE: writing N == 0 stops the clock generator, and
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causes bclk and fsync to be RECEIVED */
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#else
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uint64_t n : 32;
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uint64_t numsamp : 16;
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uint64_t deltasamp : 16;
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#endif
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} s;
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struct cvmx_pcm_clkx_gen_s cn30xx;
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struct cvmx_pcm_clkx_gen_s cn31xx;
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struct cvmx_pcm_clkx_gen_s cn50xx;
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};
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typedef union cvmx_pcm_clkx_gen cvmx_pcm_clkx_gen_t;
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#endif
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