04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
376 lines
14 KiB
C
376 lines
14 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-srxx-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon srxx.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_SRXX_TYPEDEFS_H__
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#define __CVMX_SRXX_TYPEDEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_SRXX_COM_CTL(unsigned long block_id)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
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cvmx_warn("CVMX_SRXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
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return CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull;
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}
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#else
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#define CVMX_SRXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000200ull) + ((block_id) & 1) * 0x8000000ull)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_SRXX_IGN_RX_FULL(unsigned long block_id)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
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cvmx_warn("CVMX_SRXX_IGN_RX_FULL(%lu) is invalid on this chip\n", block_id);
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return CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull;
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}
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#else
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#define CVMX_SRXX_IGN_RX_FULL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000218ull) + ((block_id) & 1) * 0x8000000ull)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_SRXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
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cvmx_warn("CVMX_SRXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
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return CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
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}
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#else
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#define CVMX_SRXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000000ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_SRXX_SPI4_STAT(unsigned long block_id)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
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cvmx_warn("CVMX_SRXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
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return CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull;
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}
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#else
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#define CVMX_SRXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000208ull) + ((block_id) & 1) * 0x8000000ull)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_SRXX_SW_TICK_CTL(unsigned long block_id)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
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cvmx_warn("CVMX_SRXX_SW_TICK_CTL(%lu) is invalid on this chip\n", block_id);
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return CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull;
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}
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#else
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#define CVMX_SRXX_SW_TICK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000220ull) + ((block_id) & 1) * 0x8000000ull)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_SRXX_SW_TICK_DAT(unsigned long block_id)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
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cvmx_warn("CVMX_SRXX_SW_TICK_DAT(%lu) is invalid on this chip\n", block_id);
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return CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull;
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}
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#else
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#define CVMX_SRXX_SW_TICK_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000228ull) + ((block_id) & 1) * 0x8000000ull)
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#endif
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/**
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* cvmx_srx#_com_ctl
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*
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* SRX_COM_CTL - Spi receive common control
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*
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*
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* Notes:
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* Restrictions:
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* Both the calendar table and the LEN and M parameters must be completely
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* setup before writing the Interface enable (INF_EN) and Status channel
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* enabled (ST_EN) asserted.
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*/
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union cvmx_srxx_com_ctl
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{
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uint64_t u64;
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struct cvmx_srxx_com_ctl_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_8_63 : 56;
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uint64_t prts : 4; /**< Number of ports in the receiver (write: ports - 1)
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- 0: 1 port
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- 1: 2 ports
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- 2: 3 ports
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- ...
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- 15: 16 ports */
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uint64_t st_en : 1; /**< Status channel enabled
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This is to allow configs without a status channel.
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This bit should not be modified once the
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interface is enabled. */
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uint64_t reserved_1_2 : 2;
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uint64_t inf_en : 1; /**< Interface enable
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The master switch that enables the entire
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interface. SRX will not validiate any data until
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this bit is set. This bit should not be modified
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once the interface is enabled. */
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#else
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uint64_t inf_en : 1;
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uint64_t reserved_1_2 : 2;
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uint64_t st_en : 1;
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uint64_t prts : 4;
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uint64_t reserved_8_63 : 56;
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#endif
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} s;
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struct cvmx_srxx_com_ctl_s cn38xx;
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struct cvmx_srxx_com_ctl_s cn38xxp2;
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struct cvmx_srxx_com_ctl_s cn58xx;
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struct cvmx_srxx_com_ctl_s cn58xxp1;
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};
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typedef union cvmx_srxx_com_ctl cvmx_srxx_com_ctl_t;
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/**
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* cvmx_srx#_ign_rx_full
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*
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* SRX_IGN_RX_FULL - Ignore RX FIFO backpressure
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*
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*
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* Notes:
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* * IGNORE
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* If a device can not or should not assert backpressure, then setting DROP
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* will force STARVING status on the status channel for all ports. This
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* eliminates any back pressure from N2.
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*
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* This implies that it's ok drop packets when the FIFOS fill up.
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*
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* A side effect of this mode is that the TPA Watcher will effectively be
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* disabled. Since the DROP mode forces all TPA lines asserted, the TPA
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* Watcher will never find a cycle where the TPA for the selected port is
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* deasserted in order to increment its count.
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*/
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union cvmx_srxx_ign_rx_full
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{
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uint64_t u64;
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struct cvmx_srxx_ign_rx_full_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_16_63 : 48;
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uint64_t ignore : 16; /**< This port should ignore backpressure hints from
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GMX when the RX FIFO fills up
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- 0: Use GMX backpressure
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- 1: Ignore GMX backpressure */
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#else
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uint64_t ignore : 16;
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uint64_t reserved_16_63 : 48;
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#endif
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} s;
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struct cvmx_srxx_ign_rx_full_s cn38xx;
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struct cvmx_srxx_ign_rx_full_s cn38xxp2;
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struct cvmx_srxx_ign_rx_full_s cn58xx;
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struct cvmx_srxx_ign_rx_full_s cn58xxp1;
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};
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typedef union cvmx_srxx_ign_rx_full cvmx_srxx_ign_rx_full_t;
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/**
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* cvmx_srx#_spi4_cal#
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*
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* specify the RSL base addresses for the block
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* SRX_SPI4_CAL - Spi4 Calender table
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* direct_calendar_write / direct_calendar_read
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*
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* Notes:
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* There are 32 calendar table CSR's, each containing 4 entries for a
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* total of 128 entries. In the above definition...
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*
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* n = calendar table offset * 4
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*
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* Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
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* (with n == 0). Offset 0x10 is the 16th entry in the calendar table
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* and would contain entries (16*4) = 64, 65, 66, and 67.
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*
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* Restrictions:
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* Calendar table entry accesses (read or write) can only occur
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* if the interface is disabled. All other accesses will be
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* unpredictable.
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*
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* Both the calendar table and the LEN and M parameters must be
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* completely setup before writing the Interface enable (INF_EN) and
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* Status channel enabled (ST_EN) asserted.
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*/
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union cvmx_srxx_spi4_calx
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{
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uint64_t u64;
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struct cvmx_srxx_spi4_calx_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_17_63 : 47;
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uint64_t oddpar : 1; /**< Odd parity over SRX_SPI4_CAL[15:0]
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(^SRX_SPI4_CAL[16:0] === 1'b1) | $NS NS */
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uint64_t prt3 : 4; /**< Status for port n+3 */
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uint64_t prt2 : 4; /**< Status for port n+2 */
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uint64_t prt1 : 4; /**< Status for port n+1 */
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uint64_t prt0 : 4; /**< Status for port n+0 */
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#else
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uint64_t prt0 : 4;
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uint64_t prt1 : 4;
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uint64_t prt2 : 4;
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uint64_t prt3 : 4;
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uint64_t oddpar : 1;
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uint64_t reserved_17_63 : 47;
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#endif
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} s;
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struct cvmx_srxx_spi4_calx_s cn38xx;
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struct cvmx_srxx_spi4_calx_s cn38xxp2;
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struct cvmx_srxx_spi4_calx_s cn58xx;
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struct cvmx_srxx_spi4_calx_s cn58xxp1;
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};
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typedef union cvmx_srxx_spi4_calx cvmx_srxx_spi4_calx_t;
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/**
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* cvmx_srx#_spi4_stat
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*
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* SRX_SPI4_STAT - Spi4 status channel control
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*
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*
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* Notes:
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* Restrictions:
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* Both the calendar table and the LEN and M parameters must be
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* completely setup before writing the Interface enable (INF_EN) and
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* Status channel enabled (ST_EN) asserted.
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*
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* Current rev only supports LVTTL status IO
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*/
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union cvmx_srxx_spi4_stat
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{
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uint64_t u64;
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struct cvmx_srxx_spi4_stat_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_16_63 : 48;
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uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */
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uint64_t reserved_7_7 : 1;
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uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */
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#else
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uint64_t len : 7;
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uint64_t reserved_7_7 : 1;
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uint64_t m : 8;
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uint64_t reserved_16_63 : 48;
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#endif
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} s;
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struct cvmx_srxx_spi4_stat_s cn38xx;
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struct cvmx_srxx_spi4_stat_s cn38xxp2;
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struct cvmx_srxx_spi4_stat_s cn58xx;
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struct cvmx_srxx_spi4_stat_s cn58xxp1;
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};
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typedef union cvmx_srxx_spi4_stat cvmx_srxx_spi4_stat_t;
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/**
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* cvmx_srx#_sw_tick_ctl
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*
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* SRX_SW_TICK_CTL - Create a software tick of Spi4 data. A write to this register will create a data tick.
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*
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*/
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union cvmx_srxx_sw_tick_ctl
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{
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uint64_t u64;
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struct cvmx_srxx_sw_tick_ctl_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t reserved_14_63 : 50;
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uint64_t eop : 1; /**< SW Tick EOP
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(PASS3 only) */
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uint64_t sop : 1; /**< SW Tick SOP
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(PASS3 only) */
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uint64_t mod : 4; /**< SW Tick MOD - valid byte count
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(PASS3 only) */
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uint64_t opc : 4; /**< SW Tick ERR - packet had an error
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(PASS3 only) */
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uint64_t adr : 4; /**< SW Tick port address
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(PASS3 only) */
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#else
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uint64_t adr : 4;
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uint64_t opc : 4;
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uint64_t mod : 4;
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uint64_t sop : 1;
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uint64_t eop : 1;
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uint64_t reserved_14_63 : 50;
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#endif
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} s;
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struct cvmx_srxx_sw_tick_ctl_s cn38xx;
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struct cvmx_srxx_sw_tick_ctl_s cn58xx;
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struct cvmx_srxx_sw_tick_ctl_s cn58xxp1;
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};
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typedef union cvmx_srxx_sw_tick_ctl cvmx_srxx_sw_tick_ctl_t;
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/**
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* cvmx_srx#_sw_tick_dat
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*
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* SRX_SW_TICK_DAT - Create a software tick of Spi4 data
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*
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*/
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union cvmx_srxx_sw_tick_dat
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{
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uint64_t u64;
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struct cvmx_srxx_sw_tick_dat_s
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{
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#if __BYTE_ORDER == __BIG_ENDIAN
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uint64_t dat : 64; /**< Data tick when SRX_SW_TICK_CTL is written
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(PASS3 only) */
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#else
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uint64_t dat : 64;
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#endif
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} s;
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struct cvmx_srxx_sw_tick_dat_s cn38xx;
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struct cvmx_srxx_sw_tick_dat_s cn58xx;
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struct cvmx_srxx_sw_tick_dat_s cn58xxp1;
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};
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typedef union cvmx_srxx_sw_tick_dat cvmx_srxx_sw_tick_dat_t;
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#endif
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