04b6fa8330
facilities as well as support for the Octeon 2 family of SoCs.
XXX Note that with our antediluvian assembler, we can't support some Octeon 2
instructions and fall back to using the old ones instead.
507 lines
14 KiB
C
507 lines
14 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Interface to the TWSI / I2C bus
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*
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* <hr>$Revision: 49448 $<hr>
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*
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*/
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <linux/i2c.h>
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-twsi.h>
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#else
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#include "cvmx.h"
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#include "cvmx-twsi.h"
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#include "cvmx-csr-db.h"
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#endif
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//#define PRINT_TWSI_CONFIG
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#ifdef PRINT_TWSI_CONFIG
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#define twsi_printf printf
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#else
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#define twsi_printf(...)
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#define cvmx_csr_db_decode(...)
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#endif
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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static struct i2c_adapter *__cvmx_twsix_get_adapter(int twsi_id)
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{
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# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
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struct octeon_i2c {
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wait_queue_head_t queue;
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struct i2c_adapter adap;
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int irq;
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int twsi_freq;
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int sys_freq;
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resource_size_t twsi_phys;
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void __iomem *twsi_base;
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resource_size_t regsize;
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struct device *dev;
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int broken_irq_mode;
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};
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struct i2c_adapter *adapter;
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struct octeon_i2c *i2c;
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adapter = i2c_get_adapter(0);
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if (adapter == NULL)
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return NULL;
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i2c = container_of(adapter, struct octeon_i2c, adap);
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return &i2c[twsi_id].adap;
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#else
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return NULL;
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#endif
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}
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#endif
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/**
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* Do a twsi read from a 7 bit device address using an (optional) internal address.
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* Up to 8 bytes can be read at a time.
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*
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* @param twsi_id which Octeon TWSI bus to use
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* @param dev_addr Device address (7 bit)
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* @param internal_addr
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* Internal address. Can be 0, 1 or 2 bytes in width
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* @param num_bytes Number of data bytes to read
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* @param ia_width_bytes
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* Internal address size in bytes (0, 1, or 2)
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* @param data Pointer argument where the read data is returned.
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*
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* @return read data returned in 'data' argument
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* Number of bytes read on success
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* -1 on failure
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*/
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int cvmx_twsix_read_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t *data)
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{
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
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struct i2c_adapter *adapter;
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u8 data_buf[8];
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u8 addr_buf[8];
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struct i2c_msg msg[2];
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uint64_t r;
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int i, j;
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if (ia_width_bytes == 0)
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return cvmx_twsix_read(twsi_id, dev_addr, num_bytes, data);
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BUG_ON(ia_width_bytes > 2);
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BUG_ON(num_bytes > 8 || num_bytes < 1);
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adapter = __cvmx_twsix_get_adapter(twsi_id);
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if (adapter == NULL)
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return -1;
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for (j = 0, i = ia_width_bytes - 1; i >= 0; i--, j++)
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addr_buf[j] = (u8)(internal_addr >> (i * 8));
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msg[0].addr = dev_addr;
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msg[0].flags = 0;
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msg[0].len = ia_width_bytes;
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msg[0].buf = addr_buf;
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msg[1].addr = dev_addr;
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msg[1].flags = I2C_M_RD;
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msg[1].len = num_bytes;
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msg[1].buf = data_buf;
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i = i2c_transfer(adapter, msg, 2);
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i2c_put_adapter(adapter);
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if (i == 2) {
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r = 0;
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for (i = 0; i < num_bytes; i++)
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r = (r << 8) | data_buf[i];
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*data = r;
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return num_bytes;
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} else {
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return -1;
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}
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# else
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BUG(); /* The I2C driver is not compiled in */
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# endif
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#else
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cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
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cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
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if (num_bytes < 1 || num_bytes > 8 || !data || ia_width_bytes < 0 || ia_width_bytes > 2)
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return -1;
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twsi_ext.u64 = 0;
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sw_twsi_val.u64 = 0;
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sw_twsi_val.s.v = 1;
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sw_twsi_val.s.r = 1;
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sw_twsi_val.s.sovr = 1;
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sw_twsi_val.s.size = num_bytes - 1;
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sw_twsi_val.s.a = dev_addr;
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if (ia_width_bytes > 0) {
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sw_twsi_val.s.op = 1;
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sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
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sw_twsi_val.s.eop_ia = internal_addr & 0x7;
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}
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if (ia_width_bytes == 2) {
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sw_twsi_val.s.eia = 1;
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twsi_ext.s.ia = internal_addr >> 8;
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cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
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}
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cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
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;
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twsi_printf("Results:\n");
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cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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if (!sw_twsi_val.s.r)
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return -1;
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*data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
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if (num_bytes > 4) {
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twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
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*data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
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}
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return num_bytes;
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#endif
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}
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/**
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* Read from a TWSI device (7 bit device address only) without generating any
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* internal addresses.
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* Read from 1-8 bytes and returns them in the data pointer.
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*
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* @param twsi_id TWSI interface on Octeon to use
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* @param dev_addr TWSI device address (7 bit only)
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* @param num_bytes number of bytes to read
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* @param data Pointer to data read from TWSI device
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*
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* @return Number of bytes read on success
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* -1 on error
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*/
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int cvmx_twsix_read(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t *data)
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{
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
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struct i2c_adapter *adapter;
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u8 data_buf[8];
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struct i2c_msg msg[1];
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uint64_t r;
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int i;
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BUG_ON(num_bytes > 8 || num_bytes < 1);
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adapter = __cvmx_twsix_get_adapter(twsi_id);
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if (adapter == NULL)
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return -1;
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msg[0].addr = dev_addr;
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msg[0].flags = I2C_M_RD;
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msg[0].len = num_bytes;
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msg[0].buf = data_buf;
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i = i2c_transfer(adapter, msg, 1);
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i2c_put_adapter(adapter);
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if (i == 1) {
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r = 0;
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for (i = 0; i < num_bytes; i++)
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r = (r << 8) | data_buf[i];
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*data = r;
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return num_bytes;
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} else {
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return -1;
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}
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# else
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BUG(); /* The I2C driver is not compiled in */
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# endif
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#else
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cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
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cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
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if (num_bytes > 8 || num_bytes < 1)
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return -1;
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sw_twsi_val.u64 = 0;
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sw_twsi_val.s.v = 1;
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sw_twsi_val.s.r = 1;
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sw_twsi_val.s.a = dev_addr;
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sw_twsi_val.s.sovr = 1;
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sw_twsi_val.s.size = num_bytes - 1;
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cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
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;
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twsi_printf("Results:\n");
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cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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if (!sw_twsi_val.s.r)
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return -1;
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*data = (sw_twsi_val.s.d & (0xFFFFFFFF >> (32 - num_bytes*8)));
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if (num_bytes > 4) {
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twsi_ext.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id));
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*data |= ((unsigned long long)(twsi_ext.s.d & (0xFFFFFFFF >> (32 - num_bytes*8))) << 32);
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}
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return num_bytes;
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#endif
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}
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/**
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* Perform a twsi write operation to a 7 bit device address.
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*
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* Note that many eeprom devices have page restrictions regarding address boundaries
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* that can be crossed in one write operation. This is device dependent, and this routine
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* does nothing in this regard.
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* This command does not generate any internal addressess.
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*
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* @param twsi_id Octeon TWSI interface to use
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* @param dev_addr TWSI device address
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* @param num_bytes Number of bytes to write (between 1 and 8 inclusive)
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* @param data Data to write
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*
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* @return 0 on success
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* -1 on failure
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*/
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int cvmx_twsix_write(int twsi_id, uint8_t dev_addr, int num_bytes, uint64_t data)
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{
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
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struct i2c_adapter *adapter;
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u8 data_buf[8];
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struct i2c_msg msg[1];
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int i, j;
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BUG_ON(num_bytes > 8 || num_bytes < 1);
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adapter = __cvmx_twsix_get_adapter(twsi_id);
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if (adapter == NULL)
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return -1;
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for (j = 0, i = num_bytes - 1; i >= 0; i--, j++)
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data_buf[j] = (u8)(data >> (i * 8));
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msg[1].addr = dev_addr;
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msg[1].flags = 0;
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msg[1].len = num_bytes;
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msg[1].buf = data_buf;
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i = i2c_transfer(adapter, msg, 1);
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i2c_put_adapter(adapter);
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if (i == 1)
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return num_bytes;
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else
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return -1;
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# else
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BUG(); /* The I2C driver is not compiled in */
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# endif
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#else
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cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
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if (num_bytes > 8 || num_bytes < 1)
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return -1;
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sw_twsi_val.u64 = 0;
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sw_twsi_val.s.v = 1;
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sw_twsi_val.s.a = dev_addr;
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sw_twsi_val.s.d = data & 0xffffffff;
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sw_twsi_val.s.sovr = 1;
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sw_twsi_val.s.size = num_bytes - 1;
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if (num_bytes > 4) {
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/* Upper four bytes go into a separate register */
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cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
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twsi_ext.u64 = 0;
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twsi_ext.s.d = data >> 32;
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cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
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}
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cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
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;
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twsi_printf("Results:\n");
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cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
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if (!sw_twsi_val.s.r)
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return -1;
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return 0;
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#endif
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}
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/**
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* Write 1-8 bytes to a TWSI device using an internal address.
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*
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* @param twsi_id which TWSI interface on Octeon to use
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* @param dev_addr TWSI device address (7 bit only)
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* @param internal_addr
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* TWSI internal address (0, 8, or 16 bits)
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* @param num_bytes Number of bytes to write (1-8)
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* @param ia_width_bytes
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* internal address width, in bytes (0, 1, 2)
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* @param data Data to write. Data is written MSB first on the twsi bus, and only the lower
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* num_bytes bytes of the argument are valid. (If a 2 byte write is done, only
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* the low 2 bytes of the argument is used.
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*
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* @return Number of bytes read on success,
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* -1 on error
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*/
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int cvmx_twsix_write_ia(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data)
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{
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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# if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
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struct i2c_adapter *adapter;
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u8 data_buf[8];
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u8 addr_buf[8];
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struct i2c_msg msg[2];
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int i, j;
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if (ia_width_bytes == 0)
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return cvmx_twsix_write(twsi_id, dev_addr, num_bytes, data);
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BUG_ON(ia_width_bytes > 2);
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BUG_ON(num_bytes > 8 || num_bytes < 1);
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adapter = __cvmx_twsix_get_adapter(twsi_id);
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if (adapter == NULL)
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return -1;
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for (j = 0, i = ia_width_bytes - 1; i >= 0; i--, j++)
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addr_buf[j] = (u8)(internal_addr >> (i * 8));
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for (j = 0, i = num_bytes - 1; i >= 0; i--, j++)
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data_buf[j] = (u8)(data >> (i * 8));
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msg[0].addr = dev_addr;
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msg[0].flags = 0;
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msg[0].len = ia_width_bytes;
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msg[0].buf = addr_buf;
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msg[1].addr = dev_addr;
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msg[1].flags = 0;
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msg[1].len = num_bytes;
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msg[1].buf = data_buf;
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i = i2c_transfer(adapter, msg, 2);
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i2c_put_adapter(adapter);
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if (i == 2) {
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/* Poll until reads succeed, or polling times out */
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int to = 100;
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while (to-- > 0) {
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uint64_t data;
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if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)
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break;
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}
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}
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if (i == 2)
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return num_bytes;
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else
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return -1;
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# else
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BUG(); /* The I2C driver is not compiled in */
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# endif
|
|
#else
|
|
cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
|
|
cvmx_mio_twsx_sw_twsi_ext_t twsi_ext;
|
|
int to;
|
|
|
|
if (num_bytes < 1 || num_bytes > 8 || ia_width_bytes < 0 || ia_width_bytes > 2)
|
|
return -1;
|
|
|
|
twsi_ext.u64 = 0;
|
|
|
|
sw_twsi_val.u64 = 0;
|
|
sw_twsi_val.s.v = 1;
|
|
sw_twsi_val.s.sovr = 1;
|
|
sw_twsi_val.s.size = num_bytes - 1;
|
|
sw_twsi_val.s.a = dev_addr;
|
|
sw_twsi_val.s.d = 0xFFFFFFFF & data;
|
|
|
|
if (ia_width_bytes > 0) {
|
|
sw_twsi_val.s.op = 1;
|
|
sw_twsi_val.s.ia = (internal_addr >> 3) & 0x1f;
|
|
sw_twsi_val.s.eop_ia = internal_addr & 0x7;
|
|
}
|
|
if (ia_width_bytes == 2) {
|
|
sw_twsi_val.s.eia = 1;
|
|
twsi_ext.s.ia = internal_addr >> 8;
|
|
}
|
|
if (num_bytes > 4)
|
|
twsi_ext.s.d = data >> 32;
|
|
|
|
twsi_printf("%s: twsi_id=%x, dev_addr=%x, internal_addr=%x\n\tnum_bytes=%d, ia_width_bytes=%d, data=%lx\n",
|
|
__FUNCTION__, twsi_id, dev_addr, internal_addr, num_bytes, ia_width_bytes, data);
|
|
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
|
|
cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI_EXT(twsi_id), twsi_ext.u64);
|
|
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
|
|
cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
|
|
while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
|
|
;
|
|
twsi_printf("Results:\n");
|
|
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
|
|
|
|
/* Poll until reads succeed, or polling times out */
|
|
to = 100;
|
|
while (to-- > 0) {
|
|
uint64_t data;
|
|
if (cvmx_twsix_read(twsi_id, dev_addr, 1, &data) >= 0)
|
|
break;
|
|
}
|
|
if (to <= 0)
|
|
return -1;
|
|
|
|
return num_bytes;
|
|
#endif
|
|
}
|