d521c6b9c4
functions are implemented with CMPXCHG8B instruction where it is available, i. e., all Pentium-class and later processors. Note this instruction is also used for atomic_store_rel_64() because a simple XCHG-like instruction for 64-bit memory access does not exist, unfortunately. If the processor lacks the instruction, i. e., 80486-class CPUs, two 32-bit load/store are performed with interrupt temporarily disabled, assuming it does not support SMP. Although this assumption may be little naive, it is true in reality. This implementation is inspired by Linux.
574 lines
17 KiB
C
574 lines
17 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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#ifndef _SYS_CDEFS_H_
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#error this file needs sys/cdefs.h as a prerequisite
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#endif
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#define mb() __asm __volatile("lock; addl $0,(%%esp)" : : : "memory")
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#define wmb() __asm __volatile("lock; addl $0,(%%esp)" : : : "memory")
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#define rmb() __asm __volatile("lock; addl $0,(%%esp)" : : : "memory")
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/*
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* Various simple operations on memory, each of which is atomic in the
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* presence of interrupts and multiple processors.
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*
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* atomic_set_char(P, V) (*(u_char *)(P) |= (V))
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* atomic_clear_char(P, V) (*(u_char *)(P) &= ~(V))
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* atomic_add_char(P, V) (*(u_char *)(P) += (V))
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* atomic_subtract_char(P, V) (*(u_char *)(P) -= (V))
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*
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* atomic_set_short(P, V) (*(u_short *)(P) |= (V))
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* atomic_clear_short(P, V) (*(u_short *)(P) &= ~(V))
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* atomic_add_short(P, V) (*(u_short *)(P) += (V))
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* atomic_subtract_short(P, V) (*(u_short *)(P) -= (V))
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*
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* atomic_set_int(P, V) (*(u_int *)(P) |= (V))
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* atomic_clear_int(P, V) (*(u_int *)(P) &= ~(V))
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* atomic_add_int(P, V) (*(u_int *)(P) += (V))
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* atomic_subtract_int(P, V) (*(u_int *)(P) -= (V))
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* atomic_readandclear_int(P) (return (*(u_int *)(P)); *(u_int *)(P) = 0;)
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*
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* atomic_set_long(P, V) (*(u_long *)(P) |= (V))
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* atomic_clear_long(P, V) (*(u_long *)(P) &= ~(V))
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* atomic_add_long(P, V) (*(u_long *)(P) += (V))
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* atomic_subtract_long(P, V) (*(u_long *)(P) -= (V))
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* atomic_readandclear_long(P) (return (*(u_long *)(P)); *(u_long *)(P) = 0;)
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*/
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/*
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* The above functions are expanded inline in the statically-linked
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* kernel. Lock prefixes are generated if an SMP kernel is being
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* built.
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*
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* Kernel modules call real functions which are built into the kernel.
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* This allows kernel modules to be portable between UP and SMP systems.
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*/
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#if defined(KLD_MODULE) || !defined(__GNUCLIKE_ASM)
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#define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \
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void atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v); \
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void atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v)
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int atomic_cmpset_int(volatile u_int *dst, u_int expect, u_int src);
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u_int atomic_fetchadd_int(volatile u_int *p, u_int v);
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#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \
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u_##TYPE atomic_load_acq_##TYPE(volatile u_##TYPE *p); \
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void atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v)
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#else /* !KLD_MODULE && __GNUCLIKE_ASM */
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/*
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* For userland, always use lock prefixes so that the binaries will run
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* on both SMP and !SMP systems.
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*/
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#if defined(SMP) || !defined(_KERNEL)
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#define MPLOCKED "lock ; "
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#else
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#define MPLOCKED
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#endif
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/*
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* The assembly is volatilized to avoid code chunk removal by the compiler.
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* GCC aggressively reorders operations and memory clobbering is necessary
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* in order to avoid that for memory barriers.
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*/
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#define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \
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static __inline void \
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atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
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{ \
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__asm __volatile(MPLOCKED OP \
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: "=m" (*p) \
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: CONS (V), "m" (*p) \
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: "cc"); \
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} \
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\
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static __inline void \
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atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
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{ \
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__asm __volatile(MPLOCKED OP \
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: "=m" (*p) \
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: CONS (V), "m" (*p) \
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: "memory", "cc"); \
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} \
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struct __hack
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#if defined(_KERNEL) && !defined(WANT_FUNCTIONS)
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/* I486 does not support SMP or CMPXCHG8B. */
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static __inline uint64_t
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atomic_load_acq_64_i386(volatile uint64_t *p)
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{
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volatile uint32_t *high, *low;
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uint64_t res;
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low = (volatile uint32_t *)p;
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high = (volatile uint32_t *)p + 1;
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__asm __volatile(
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" pushfl ; "
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" cli ; "
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" movl %1,%%eax ; "
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" movl %2,%%edx ; "
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" popfl"
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: "=&A" (res) /* 0 */
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: "m" (*low), /* 1 */
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"m" (*high) /* 2 */
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: "memory");
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return (res);
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}
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static __inline void
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atomic_store_rel_64_i386(volatile uint64_t *p, uint64_t v)
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{
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volatile uint32_t *high, *low;
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low = (volatile uint32_t *)p;
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high = (volatile uint32_t *)p + 1;
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__asm __volatile(
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" pushfl ; "
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" cli ; "
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" movl %%eax,%0 ; "
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" movl %%edx,%1 ; "
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" popfl"
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: "=m" (*low), /* 0 */
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"=m" (*high) /* 1 */
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: "A" (v) /* 2 */
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: "memory");
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}
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static __inline uint64_t
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atomic_load_acq_64_i586(volatile uint64_t *p)
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{
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uint64_t res;
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__asm __volatile(
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" movl %%ebx,%%eax ; "
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" movl %%ecx,%%edx ; "
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" " MPLOCKED " "
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" cmpxchg8b %2"
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: "=&A" (res), /* 0 */
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"=m" (*p) /* 1 */
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: "m" (*p) /* 2 */
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: "memory", "cc");
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return (res);
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}
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static __inline void
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atomic_store_rel_64_i586(volatile uint64_t *p, uint64_t v)
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{
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__asm __volatile(
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" movl %%eax,%%ebx ; "
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" movl %%edx,%%ecx ; "
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"1: "
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" " MPLOCKED " "
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" cmpxchg8b %2 ; "
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" jne 1b"
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: "=m" (*p), /* 0 */
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"+A" (v) /* 1 */
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: "m" (*p) /* 2 */
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: "ebx", "ecx", "memory", "cc");
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}
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#endif /* _KERNEL && !WANT_FUNCTIONS */
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/*
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* Atomic compare and set, used by the mutex functions
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*
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* if (*dst == expect) *dst = src (all 32 bit words)
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*
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* Returns 0 on failure, non-zero on success
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*/
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#ifdef CPU_DISABLE_CMPXCHG
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static __inline int
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atomic_cmpset_int(volatile u_int *dst, u_int expect, u_int src)
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{
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u_char res;
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__asm __volatile(
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" pushfl ; "
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" cli ; "
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" cmpl %3,%4 ; "
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" jne 1f ; "
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" movl %2,%1 ; "
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"1: "
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" sete %0 ; "
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" popfl ; "
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"# atomic_cmpset_int"
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: "=q" (res), /* 0 */
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"=m" (*dst) /* 1 */
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: "r" (src), /* 2 */
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"r" (expect), /* 3 */
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"m" (*dst) /* 4 */
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: "memory");
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return (res);
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}
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#else /* !CPU_DISABLE_CMPXCHG */
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static __inline int
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atomic_cmpset_int(volatile u_int *dst, u_int expect, u_int src)
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{
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u_char res;
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__asm __volatile(
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" " MPLOCKED " "
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" cmpxchgl %2,%1 ; "
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" sete %0 ; "
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"1: "
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"# atomic_cmpset_int"
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: "=a" (res), /* 0 */
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"=m" (*dst) /* 1 */
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: "r" (src), /* 2 */
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"a" (expect), /* 3 */
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"m" (*dst) /* 4 */
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: "memory", "cc");
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return (res);
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}
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#endif /* CPU_DISABLE_CMPXCHG */
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/*
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* Atomically add the value of v to the integer pointed to by p and return
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* the previous value of *p.
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*/
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static __inline u_int
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atomic_fetchadd_int(volatile u_int *p, u_int v)
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{
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__asm __volatile(
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" " MPLOCKED " "
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" xaddl %0, %1 ; "
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"# atomic_fetchadd_int"
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: "+r" (v), /* 0 (result) */
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"=m" (*p) /* 1 */
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: "m" (*p) /* 2 */
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: "cc");
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return (v);
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}
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#if defined(_KERNEL) && !defined(SMP)
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/*
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* We assume that a = b will do atomic loads and stores. However, on a
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* PentiumPro or higher, reads may pass writes, so for that case we have
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* to use a serializing instruction (i.e. with LOCK) to do the load in
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* SMP kernels. For UP kernels, however, the cache of the single processor
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* is always consistent, so we only need to take care of compiler.
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*/
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#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \
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static __inline u_##TYPE \
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atomic_load_acq_##TYPE(volatile u_##TYPE *p) \
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{ \
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u_##TYPE tmp; \
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\
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tmp = *p; \
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__asm __volatile("" : : : "memory"); \
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return (tmp); \
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} \
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\
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static __inline void \
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atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
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{ \
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__asm __volatile("" : : : "memory"); \
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*p = v; \
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} \
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struct __hack
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#else /* !(_KERNEL && !SMP) */
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#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \
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static __inline u_##TYPE \
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atomic_load_acq_##TYPE(volatile u_##TYPE *p) \
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{ \
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u_##TYPE res; \
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\
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__asm __volatile(MPLOCKED LOP \
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: "=a" (res), /* 0 */ \
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"=m" (*p) /* 1 */ \
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: "m" (*p) /* 2 */ \
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: "memory", "cc"); \
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\
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return (res); \
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} \
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\
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/* \
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* The XCHG instruction asserts LOCK automagically. \
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*/ \
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static __inline void \
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atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
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{ \
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__asm __volatile(SOP \
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: "=m" (*p), /* 0 */ \
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"+r" (v) /* 1 */ \
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: "m" (*p) /* 2 */ \
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: "memory"); \
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} \
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struct __hack
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#endif /* _KERNEL && !SMP */
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#endif /* KLD_MODULE || !__GNUCLIKE_ASM */
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ATOMIC_ASM(set, char, "orb %b1,%0", "iq", v);
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ATOMIC_ASM(clear, char, "andb %b1,%0", "iq", ~v);
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ATOMIC_ASM(add, char, "addb %b1,%0", "iq", v);
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ATOMIC_ASM(subtract, char, "subb %b1,%0", "iq", v);
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ATOMIC_ASM(set, short, "orw %w1,%0", "ir", v);
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ATOMIC_ASM(clear, short, "andw %w1,%0", "ir", ~v);
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ATOMIC_ASM(add, short, "addw %w1,%0", "ir", v);
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ATOMIC_ASM(subtract, short, "subw %w1,%0", "ir", v);
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ATOMIC_ASM(set, int, "orl %1,%0", "ir", v);
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ATOMIC_ASM(clear, int, "andl %1,%0", "ir", ~v);
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ATOMIC_ASM(add, int, "addl %1,%0", "ir", v);
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ATOMIC_ASM(subtract, int, "subl %1,%0", "ir", v);
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ATOMIC_ASM(set, long, "orl %1,%0", "ir", v);
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ATOMIC_ASM(clear, long, "andl %1,%0", "ir", ~v);
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ATOMIC_ASM(add, long, "addl %1,%0", "ir", v);
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ATOMIC_ASM(subtract, long, "subl %1,%0", "ir", v);
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ATOMIC_STORE_LOAD(char, "cmpxchgb %b0,%1", "xchgb %b1,%0");
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ATOMIC_STORE_LOAD(short,"cmpxchgw %w0,%1", "xchgw %w1,%0");
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ATOMIC_STORE_LOAD(int, "cmpxchgl %0,%1", "xchgl %1,%0");
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ATOMIC_STORE_LOAD(long, "cmpxchgl %0,%1", "xchgl %1,%0");
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#undef ATOMIC_ASM
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#undef ATOMIC_STORE_LOAD
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#ifndef WANT_FUNCTIONS
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#ifdef _KERNEL
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extern uint64_t (*atomic_load_acq_64)(volatile uint64_t *);
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extern void (*atomic_store_rel_64)(volatile uint64_t *, uint64_t);
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#endif
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static __inline int
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atomic_cmpset_long(volatile u_long *dst, u_long expect, u_long src)
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{
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return (atomic_cmpset_int((volatile u_int *)dst, (u_int)expect,
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(u_int)src));
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}
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static __inline u_long
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atomic_fetchadd_long(volatile u_long *p, u_long v)
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{
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return (atomic_fetchadd_int((volatile u_int *)p, (u_int)v));
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}
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/* Read the current value and store a zero in the destination. */
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#ifdef __GNUCLIKE_ASM
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static __inline u_int
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atomic_readandclear_int(volatile u_int *addr)
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{
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u_int res;
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res = 0;
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__asm __volatile(
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" xchgl %1,%0 ; "
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"# atomic_readandclear_int"
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: "+r" (res), /* 0 */
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"=m" (*addr) /* 1 */
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: "m" (*addr));
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return (res);
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}
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static __inline u_long
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atomic_readandclear_long(volatile u_long *addr)
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{
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u_long res;
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res = 0;
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__asm __volatile(
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" xchgl %1,%0 ; "
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"# atomic_readandclear_long"
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: "+r" (res), /* 0 */
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"=m" (*addr) /* 1 */
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: "m" (*addr));
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return (res);
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}
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#else /* !__GNUCLIKE_ASM */
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u_int atomic_readandclear_int(volatile u_int *addr);
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u_long atomic_readandclear_long(volatile u_long *addr);
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#endif /* __GNUCLIKE_ASM */
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#define atomic_set_acq_char atomic_set_barr_char
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#define atomic_set_rel_char atomic_set_barr_char
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#define atomic_clear_acq_char atomic_clear_barr_char
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#define atomic_clear_rel_char atomic_clear_barr_char
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#define atomic_add_acq_char atomic_add_barr_char
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#define atomic_add_rel_char atomic_add_barr_char
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#define atomic_subtract_acq_char atomic_subtract_barr_char
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#define atomic_subtract_rel_char atomic_subtract_barr_char
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#define atomic_set_acq_short atomic_set_barr_short
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#define atomic_set_rel_short atomic_set_barr_short
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#define atomic_clear_acq_short atomic_clear_barr_short
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#define atomic_clear_rel_short atomic_clear_barr_short
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#define atomic_add_acq_short atomic_add_barr_short
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#define atomic_add_rel_short atomic_add_barr_short
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#define atomic_subtract_acq_short atomic_subtract_barr_short
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#define atomic_subtract_rel_short atomic_subtract_barr_short
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#define atomic_set_acq_int atomic_set_barr_int
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#define atomic_set_rel_int atomic_set_barr_int
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#define atomic_clear_acq_int atomic_clear_barr_int
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#define atomic_clear_rel_int atomic_clear_barr_int
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#define atomic_add_acq_int atomic_add_barr_int
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#define atomic_add_rel_int atomic_add_barr_int
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#define atomic_subtract_acq_int atomic_subtract_barr_int
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#define atomic_subtract_rel_int atomic_subtract_barr_int
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#define atomic_cmpset_acq_int atomic_cmpset_int
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#define atomic_cmpset_rel_int atomic_cmpset_int
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#define atomic_set_acq_long atomic_set_barr_long
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#define atomic_set_rel_long atomic_set_barr_long
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#define atomic_clear_acq_long atomic_clear_barr_long
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#define atomic_clear_rel_long atomic_clear_barr_long
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#define atomic_add_acq_long atomic_add_barr_long
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#define atomic_add_rel_long atomic_add_barr_long
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#define atomic_subtract_acq_long atomic_subtract_barr_long
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#define atomic_subtract_rel_long atomic_subtract_barr_long
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#define atomic_cmpset_acq_long atomic_cmpset_long
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#define atomic_cmpset_rel_long atomic_cmpset_long
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/* Operations on 8-bit bytes. */
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#define atomic_set_8 atomic_set_char
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#define atomic_set_acq_8 atomic_set_acq_char
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#define atomic_set_rel_8 atomic_set_rel_char
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#define atomic_clear_8 atomic_clear_char
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#define atomic_clear_acq_8 atomic_clear_acq_char
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#define atomic_clear_rel_8 atomic_clear_rel_char
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#define atomic_add_8 atomic_add_char
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#define atomic_add_acq_8 atomic_add_acq_char
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#define atomic_add_rel_8 atomic_add_rel_char
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#define atomic_subtract_8 atomic_subtract_char
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#define atomic_subtract_acq_8 atomic_subtract_acq_char
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#define atomic_subtract_rel_8 atomic_subtract_rel_char
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#define atomic_load_acq_8 atomic_load_acq_char
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#define atomic_store_rel_8 atomic_store_rel_char
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/* Operations on 16-bit words. */
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#define atomic_set_16 atomic_set_short
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#define atomic_set_acq_16 atomic_set_acq_short
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#define atomic_set_rel_16 atomic_set_rel_short
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#define atomic_clear_16 atomic_clear_short
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#define atomic_clear_acq_16 atomic_clear_acq_short
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#define atomic_clear_rel_16 atomic_clear_rel_short
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#define atomic_add_16 atomic_add_short
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#define atomic_add_acq_16 atomic_add_acq_short
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#define atomic_add_rel_16 atomic_add_rel_short
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#define atomic_subtract_16 atomic_subtract_short
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#define atomic_subtract_acq_16 atomic_subtract_acq_short
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#define atomic_subtract_rel_16 atomic_subtract_rel_short
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#define atomic_load_acq_16 atomic_load_acq_short
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#define atomic_store_rel_16 atomic_store_rel_short
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/* Operations on 32-bit double words. */
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#define atomic_set_32 atomic_set_int
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#define atomic_set_acq_32 atomic_set_acq_int
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#define atomic_set_rel_32 atomic_set_rel_int
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#define atomic_clear_32 atomic_clear_int
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#define atomic_clear_acq_32 atomic_clear_acq_int
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#define atomic_clear_rel_32 atomic_clear_rel_int
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#define atomic_add_32 atomic_add_int
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#define atomic_add_acq_32 atomic_add_acq_int
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#define atomic_add_rel_32 atomic_add_rel_int
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#define atomic_subtract_32 atomic_subtract_int
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#define atomic_subtract_acq_32 atomic_subtract_acq_int
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#define atomic_subtract_rel_32 atomic_subtract_rel_int
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#define atomic_load_acq_32 atomic_load_acq_int
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#define atomic_store_rel_32 atomic_store_rel_int
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#define atomic_cmpset_32 atomic_cmpset_int
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#define atomic_cmpset_acq_32 atomic_cmpset_acq_int
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#define atomic_cmpset_rel_32 atomic_cmpset_rel_int
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#define atomic_readandclear_32 atomic_readandclear_int
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#define atomic_fetchadd_32 atomic_fetchadd_int
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/* Operations on pointers. */
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#define atomic_set_ptr(p, v) \
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atomic_set_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_set_acq_ptr(p, v) \
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atomic_set_acq_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_set_rel_ptr(p, v) \
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atomic_set_rel_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_clear_ptr(p, v) \
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atomic_clear_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_clear_acq_ptr(p, v) \
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atomic_clear_acq_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_clear_rel_ptr(p, v) \
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atomic_clear_rel_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_add_ptr(p, v) \
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atomic_add_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_add_acq_ptr(p, v) \
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atomic_add_acq_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_add_rel_ptr(p, v) \
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atomic_add_rel_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_subtract_ptr(p, v) \
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atomic_subtract_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_subtract_acq_ptr(p, v) \
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atomic_subtract_acq_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_subtract_rel_ptr(p, v) \
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atomic_subtract_rel_int((volatile u_int *)(p), (u_int)(v))
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#define atomic_load_acq_ptr(p) \
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atomic_load_acq_int((volatile u_int *)(p))
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#define atomic_store_rel_ptr(p, v) \
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atomic_store_rel_int((volatile u_int *)(p), (v))
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#define atomic_cmpset_ptr(dst, old, new) \
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atomic_cmpset_int((volatile u_int *)(dst), (u_int)(old), (u_int)(new))
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#define atomic_cmpset_acq_ptr(dst, old, new) \
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atomic_cmpset_acq_int((volatile u_int *)(dst), (u_int)(old), \
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(u_int)(new))
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#define atomic_cmpset_rel_ptr(dst, old, new) \
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atomic_cmpset_rel_int((volatile u_int *)(dst), (u_int)(old), \
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(u_int)(new))
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#define atomic_readandclear_ptr(p) \
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atomic_readandclear_int((volatile u_int *)(p))
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#endif /* !WANT_FUNCTIONS */
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#endif /* !_MACHINE_ATOMIC_H_ */
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