321 lines
7.9 KiB
Plaintext
321 lines
7.9 KiB
Plaintext
/*
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* Copyright (c) 2013 Ian Lepore
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* Copyright (c) 2010 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software substantially based on work developed by Semihalf
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* GlobalScale Technologies DreamPlug Device Tree Source.
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*
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* This source is for version 10 revision 01 units with NOR SPI flash.
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* These units are marked "1001" on the serial number label.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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/ {
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model = "GlobalScale Technologies Dreamplug v1001";
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compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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mpp = &MPP;
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serial0 = &serial0;
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serial1 = &serial1;
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soc = &SOC;
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sram = &SRAM;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "ARM,88FR131";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x4000>; // L1, 16K
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i-cache-size = <0x4000>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x20000000>; // 512M at 0x0
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};
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localbus@0 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "mrvl,lbc";
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bank-count = <1>;
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/* This reflects CPU decode windows setup. */
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ranges = <0x0 0x1e 0xfa000000 0x00100000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x00100000>;
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bank-width = <2>;
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device-width = <1>;
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};
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};
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SOC: soc88f6281@f1000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0xf1000000 0x00100000>;
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bus-frequency = <0>;
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PIC: pic@20200 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x20200 0x3c>;
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compatible = "mrvl,pic";
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};
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timer@20300 {
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compatible = "mrvl,timer";
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reg = <0x20300 0x30>;
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interrupts = <1>;
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interrupt-parent = <&PIC>;
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mrvl,has-wdt;
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};
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MPP: mpp@10000 {
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#pin-cells = <2>;
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compatible = "mrvl,mpp";
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reg = <0x10000 0x34>;
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pin-count = <50>;
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pin-map = <
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0 2 /* MPP[ 0]: SPI_SCn */
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1 2 /* MPP[ 1]: SPI_MOSI */
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2 2 /* MPP[ 2]: SPI_SCK */
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3 2 /* MPP[ 3]: SPI_MISO */
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4 1 /* MPP[ 4]: NF_IO[6] */
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5 1 /* MPP[ 5]: NF_IO[7] */
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6 1 /* MPP[ 6]: SYSRST_OUTn */
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7 0 /* MPP[ 7]: GPO[7] */
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8 1 /* MPP[ 8]: TW_SDA */
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9 1 /* MPP[ 9]: TW_SCK */
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10 3 /* MPP[10]: UA0_TXD */
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11 3 /* MPP[11]: US0_RXD */
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12 1 /* MPP[12]: SD_CLK */
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13 1 /* MPP[13]: SD_CMD */
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14 1 /* MPP[14]: SD_D[0] */
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15 1 /* MPP[15]: SD_D[1] */
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16 1 /* MPP[16]: SD_D[2] */
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17 1 /* MPP[17]: SD_D[3] */
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18 1 /* MPP[18]: NF_IO[0] */
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19 1 /* MPP[19]: NF_IO[1] */
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20 3 /* MPP[20]: GE1[ 0] */
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21 3 /* MPP[21]: GE1[ 1] */
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22 3 /* MPP[22]: GE1[ 2] */
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23 3 /* MPP[23]: GE1[ 3] */
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24 3 /* MPP[24]: GE1[ 4] */
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25 3 /* MPP[25]: GE1[ 5] */
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26 3 /* MPP[26]: GE1[ 6] */
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27 3 /* MPP[27]: GE1[ 7] */
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28 3 /* MPP[28]: GE1[ 8] */
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29 3 /* MPP[29]: GE1[ 9] */
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30 3 /* MPP[30]: GE1[10] */
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31 3 /* MPP[31]: GE1[11] */
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32 3 /* MPP[32]: GE1[12] */
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33 3 /* MPP[33]: GE1[13] */
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34 3 /* MPP[34]: GE1[14] */
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35 3 /* MPP[35]: GE1[15] */
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36 0 /* MPP[36]: GPIO[36] */
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37 0 /* MPP[37]: GPIO[37] */
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38 0 /* MPP[38]: GPIO[38] */
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39 0 /* MPP[39]: GPIO[39] */
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40 2 /* MPP[40]: TDM_SPI_SCK */
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41 2 /* MPP[41]: TDM_SPI_MISO */
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42 2 /* MPP[42]: TDM_SPI_MOSI */
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43 0 /* MPP[43]: GPIO[43] */
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44 0 /* MPP[44]: GPIO[44] */
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45 0 /* MPP[45]: GPIO[45] */
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46 0 /* MPP[46]: GPIO[46] */
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47 0 /* MPP[47]: GPIO[47] */
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48 0 /* MPP[48]: GPIO[48] */
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49 0 /* MPP[49]: GPIO[49] */
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>;
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};
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GPIO: gpio@10100 {
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#gpio-cells = <3>;
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compatible = "mrvl,gpio";
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reg = <0x10100 0x20>;
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gpio-controller;
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interrupts = <35 36 37 38 39 40 41>;
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interrupt-parent = <&PIC>;
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pin-count = <50>;
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};
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gpioled@0 {
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compatible = "mrvl,gpioled";
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gpios = <&GPIO 47 2 0 /* GPIO[47] BT LED: OUT */
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&GPIO 48 2 0 /* GPIO[48] WLAN LED: OUT */
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&GPIO 49 2 0>; /* GPIO[49] WLAN AP LED: OUT */
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};
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rtc@10300 {
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compatible = "mrvl,rtc";
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reg = <0x10300 0x08>;
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};
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twsi@11000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,twsi";
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reg = <0x11000 0x20>;
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interrupts = <43>;
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interrupt-parent = <&PIC>;
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};
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enet0: ethernet@72000 {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "V2";
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compatible = "mrvl,ge";
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reg = <0x72000 0x2000>;
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ranges = <0x0 0x72000 0x2000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <12 13 14 11 46>;
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interrupt-parent = <&PIC>;
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phy-handle = <&phy0>;
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,mdio";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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};
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};
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enet1: ethernet@76000 {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "V2";
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compatible = "mrvl,ge";
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reg = <0x76000 0x02000>;
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ranges = <0x0 0x76000 0x2000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <16 17 18 15 47>;
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interrupt-parent = <&PIC>;
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phy-handle = <&phy1>;
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};
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serial0: serial@12000 {
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compatible = "ns16550";
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reg = <0x12000 0x20>;
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reg-shift = <2>;
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clock-frequency = <0>;
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interrupts = <33>;
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interrupt-parent = <&PIC>;
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};
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serial1: serial@12100 {
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compatible = "ns16550";
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reg = <0x12100 0x20>;
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reg-shift = <2>;
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clock-frequency = <0>;
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interrupts = <34>;
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interrupt-parent = <&PIC>;
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};
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crypto@30000 {
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compatible = "mrvl,cesa";
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reg = <0x30000 0x1000 /* tdma base reg chan 0 */
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0x3D000 0x1000>; /* cesa base reg chan 0 */
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interrupts = <22>;
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interrupt-parent = <&PIC>;
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sram-handle = <&SRAM>;
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};
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usb@50000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x50000 0x1000>;
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interrupts = <48 19>;
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interrupt-parent = <&PIC>;
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};
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xor@60000 {
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compatible = "mrvl,xor";
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reg = <0x60000 0x1000>;
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interrupts = <5 6 7 8>;
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interrupt-parent = <&PIC>;
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};
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sata@80000 {
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compatible = "mrvl,sata";
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reg = <0x80000 0x6000>;
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interrupts = <21>;
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interrupt-parent = <&PIC>;
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};
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sdio@90000 {
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compatible = "mrvl,sdio";
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reg = <0x90000 0x134>;
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interrupts = <28>;
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interrupt-parent = <&PIC>;
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};
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};
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SRAM: sram@fd000000 {
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compatible = "mrvl,cesa-sram";
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reg = <0xfd000000 0x00100000>;
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};
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chosen {
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stdin = "serial0";
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stdout = "serial0";
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};
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};
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