19d3b47b92
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
355 lines
12 KiB
C
355 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __NLM_POE_H__
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#define __NLM_POE_H__
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/**
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* @file_name poe.h
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* @author Netlogic Microsystems
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* @brief Basic definitions of XLP Packet Order Engine
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*/
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/* POE specific registers */
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#define POE_CL0_ENQ_SPILL_BASE_LO 0x0
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#define POE_CL1_ENQ_SPILL_BASE_LO 0x2
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#define POE_CL2_ENQ_SPILL_BASE_LO 0x4
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#define POE_CL3_ENQ_SPILL_BASE_LO 0x6
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#define POE_CL4_ENQ_SPILL_BASE_LO 0x8
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#define POE_CL5_ENQ_SPILL_BASE_LO 0xa
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#define POE_CL6_ENQ_SPILL_BASE_LO 0xc
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#define POE_CL7_ENQ_SPILL_BASE_LO 0xe
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#define POE_CL0_ENQ_SPILL_BASE_HI 0x1
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#define POE_CL1_ENQ_SPILL_BASE_HI 0x3
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#define POE_CL2_ENQ_SPILL_BASE_HI 0x5
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#define POE_CL3_ENQ_SPILL_BASE_HI 0x7
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#define POE_CL4_ENQ_SPILL_BASE_HI 0x9
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#define POE_CL5_ENQ_SPILL_BASE_HI 0xb
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#define POE_CL6_ENQ_SPILL_BASE_HI 0xd
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#define POE_CL7_ENQ_SPILL_BASE_HI 0xf
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#define POE_CL0_DEQ_SPILL_BASE_LO 0x10
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#define POE_CL1_DEQ_SPILL_BASE_LO 0x12
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#define POE_CL2_DEQ_SPILL_BASE_LO 0x14
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#define POE_CL3_DEQ_SPILL_BASE_LO 0x16
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#define POE_CL4_DEQ_SPILL_BASE_LO 0x18
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#define POE_CL5_DEQ_SPILL_BASE_LO 0x1a
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#define POE_CL6_DEQ_SPILL_BASE_LO 0x1c
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#define POE_CL7_DEQ_SPILL_BASE_LO 0x1e
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#define POE_CL0_DEQ_SPILL_BASE_HI 0x11
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#define POE_CL1_DEQ_SPILL_BASE_HI 0x13
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#define POE_CL2_DEQ_SPILL_BASE_HI 0x15
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#define POE_CL3_DEQ_SPILL_BASE_HI 0x17
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#define POE_CL4_DEQ_SPILL_BASE_HI 0x19
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#define POE_CL5_DEQ_SPILL_BASE_HI 0x1b
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#define POE_CL6_DEQ_SPILL_BASE_HI 0x1d
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#define POE_CL7_DEQ_SPILL_BASE_HI 0x1f
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#define POE_MSG_STORAGE_BASE_ADDR_LO 0x20
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#define POE_MSG_STORAGE_BASE_ADDR_HI 0x21
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#define POE_FBP_BASE_ADDR_LO 0x22
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#define POE_FBP_BASE_ADDR_HI 0x23
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#define POE_CL0_ENQ_SPILL_MAXLINE_LO 0x24
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#define POE_CL1_ENQ_SPILL_MAXLINE_LO 0x25
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#define POE_CL2_ENQ_SPILL_MAXLINE_LO 0x26
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#define POE_CL3_ENQ_SPILL_MAXLINE_LO 0x27
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#define POE_CL4_ENQ_SPILL_MAXLINE_LO 0x28
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#define POE_CL5_ENQ_SPILL_MAXLINE_LO 0x29
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#define POE_CL6_ENQ_SPILL_MAXLINE_LO 0x2a
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#define POE_CL7_ENQ_SPILL_MAXLINE_LO 0x2b
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#define POE_CL0_ENQ_SPILL_MAXLINE_HI 0x2c
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#define POE_CL1_ENQ_SPILL_MAXLINE_HI 0x2d
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#define POE_CL2_ENQ_SPILL_MAXLINE_HI 0x2e
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#define POE_CL3_ENQ_SPILL_MAXLINE_HI 0x2f
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#define POE_CL4_ENQ_SPILL_MAXLINE_HI 0x30
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#define POE_CL5_ENQ_SPILL_MAXLINE_HI 0x31
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#define POE_CL6_ENQ_SPILL_MAXLINE_HI 0x32
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#define POE_CL7_ENQ_SPILL_MAXLINE_HI 0x33
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#define POE_MAX_FLOW_MSG0 0x40
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#define POE_MAX_FLOW_MSG1 0x41
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#define POE_MAX_FLOW_MSG2 0x42
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#define POE_MAX_FLOW_MSG3 0x43
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#define POE_MAX_FLOW_MSG4 0x44
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#define POE_MAX_FLOW_MSG5 0x45
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#define POE_MAX_FLOW_MSG6 0x46
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#define POE_MAX_FLOW_MSG7 0x47
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#define POE_MAX_MSG_CL0 0x48
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#define POE_MAX_MSG_CL1 0x49
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#define POE_MAX_MSG_CL2 0x4a
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#define POE_MAX_MSG_CL3 0x4b
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#define POE_MAX_MSG_CL4 0x4c
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#define POE_MAX_MSG_CL5 0x4d
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#define POE_MAX_MSG_CL6 0x4e
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#define POE_MAX_MSG_CL7 0x4f
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#define POE_MAX_LOC_BUF_STG_CL0 0x50
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#define POE_MAX_LOC_BUF_STG_CL1 0x51
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#define POE_MAX_LOC_BUF_STG_CL2 0x52
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#define POE_MAX_LOC_BUF_STG_CL3 0x53
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#define POE_MAX_LOC_BUF_STG_CL4 0x54
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#define POE_MAX_LOC_BUF_STG_CL5 0x55
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#define POE_MAX_LOC_BUF_STG_CL6 0x56
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#define POE_MAX_LOC_BUF_STG_CL7 0x57
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#define POE_ENQ_MSG_COUNT0_SIZE 0x58
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#define POE_ENQ_MSG_COUNT1_SIZE 0x59
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#define POE_ENQ_MSG_COUNT2_SIZE 0x5a
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#define POE_ENQ_MSG_COUNT3_SIZE 0x5b
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#define POE_ENQ_MSG_COUNT4_SIZE 0x5c
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#define POE_ENQ_MSG_COUNT5_SIZE 0x5d
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#define POE_ENQ_MSG_COUNT6_SIZE 0x5e
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#define POE_ENQ_MSG_COUNT7_SIZE 0x5f
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#define POE_ERR_MSG_DESCRIP_LO0 0x60
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#define POE_ERR_MSG_DESCRIP_LO1 0x62
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#define POE_ERR_MSG_DESCRIP_LO2 0x64
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#define POE_ERR_MSG_DESCRIP_LO3 0x66
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#define POE_ERR_MSG_DESCRIP_HI0 0x61
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#define POE_ERR_MSG_DESCRIP_HI1 0x63
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#define POE_ERR_MSG_DESCRIP_HI2 0x65
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#define POE_ERR_MSG_DESCRIP_HI3 0x67
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#define POE_OOO_MSG_CNT_LO 0x68
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#define POE_IN_ORDER_MSG_CNT_LO 0x69
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#define POE_LOC_BUF_STOR_CNT_LO 0x6a
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#define POE_EXT_BUF_STOR_CNT_LO 0x6b
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#define POE_LOC_BUF_ALLOC_CNT_LO 0x6c
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#define POE_EXT_BUF_ALLOC_CNT_LO 0x6d
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#define POE_OOO_MSG_CNT_HI 0x6e
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#define POE_IN_ORDER_MSG_CNT_HI 0x6f
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#define POE_LOC_BUF_STOR_CNT_HI 0x70
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#define POE_EXT_BUF_STOR_CNT_HI 0x71
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#define POE_LOC_BUF_ALLOC_CNT_HI 0x72
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#define POE_EXT_BUF_ALLOC_CNT_HI 0x73
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#define POE_MODE_ERR_FLOW_ID 0x74
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#define POE_STATISTICS_ENABLE 0x75
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#define POE_MAX_SIZE_FLOW 0x76
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#define POE_MAX_SIZE 0x77
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#define POE_FBP_SP 0x78
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#define POE_FBP_SP_EN 0x79
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#define POE_LOC_ALLOC_EN 0x7a
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#define POE_EXT_ALLOC_EN 0x7b
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#define POE_DISTR_0_DROP_CNT 0xc0
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#define POE_DISTR_1_DROP_CNT 0xc1
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#define POE_DISTR_2_DROP_CNT 0xc2
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#define POE_DISTR_3_DROP_CNT 0xc3
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#define POE_DISTR_4_DROP_CNT 0xc4
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#define POE_DISTR_5_DROP_CNT 0xc5
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#define POE_DISTR_6_DROP_CNT 0xc6
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#define POE_DISTR_7_DROP_CNT 0xc7
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#define POE_DISTR_8_DROP_CNT 0xc8
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#define POE_DISTR_9_DROP_CNT 0xc9
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#define POE_DISTR_10_DROP_CNT 0xca
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#define POE_DISTR_11_DROP_CNT 0xcb
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#define POE_DISTR_12_DROP_CNT 0xcc
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#define POE_DISTR_13_DROP_CNT 0xcd
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#define POE_DISTR_14_DROP_CNT 0xce
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#define POE_DISTR_15_DROP_CNT 0xcf
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#define POE_CLASS_0_DROP_CNT 0xd0
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#define POE_CLASS_1_DROP_CNT 0xd1
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#define POE_CLASS_2_DROP_CNT 0xd2
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#define POE_CLASS_3_DROP_CNT 0xd3
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#define POE_CLASS_4_DROP_CNT 0xd4
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#define POE_CLASS_5_DROP_CNT 0xd5
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#define POE_CLASS_6_DROP_CNT 0xd6
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#define POE_CLASS_7_DROP_CNT 0xd7
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#define POE_DISTR_C0_DROP_CNT 0xd8
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#define POE_DISTR_C1_DROP_CNT 0xd9
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#define POE_DISTR_C2_DROP_CNT 0xda
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#define POE_DISTR_C3_DROP_CNT 0xdb
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#define POE_DISTR_C4_DROP_CNT 0xdc
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#define POE_DISTR_C5_DROP_CNT 0xdd
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#define POE_DISTR_C6_DROP_CNT 0xde
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#define POE_DISTR_C7_DROP_CNT 0xdf
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#define POE_CPU_DROP_CNT 0xe0
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#define POE_MAX_FLOW_DROP_CNT 0xe1
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#define POE_INTERRUPT_VEC 0x140
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#define POE_INTERRUPT_MASK 0x141
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#define POE_FATALERR_MASK 0x142
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#define POE_IDI_CFG 0x143
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#define POE_TIMEOUT_VALUE 0x144
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#define POE_CACHE_ALLOC_EN 0x145
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#define POE_FBP_ECC_ERR_CNT 0x146
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#define POE_MSG_STRG_ECC_ERR_CNT 0x147
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#define POE_FID_INFO_ECC_ERR_CNT 0x148
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#define POE_MSG_INFO_ECC_ERR_CNT 0x149
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#define POE_LL_ECC_ERR_CNT 0x14a
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#define POE_SIZE_ECC_ERR_CNT 0x14b
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#define POE_FMN_TXCR_ECC_ERR_CNT 0x14c
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#define POE_ENQ_INSPIL_ECC_ERR_CNT 0x14d
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#define POE_ENQ_OUTSPIL_ECC_ERR_CNT 0x14e
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#define POE_DEQ_OUTSPIL_ECC_ERR_CNT 0x14f
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#define POE_ENQ_MSG_SENT 0x150
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#define POE_ENQ_MSG_CNT 0x151
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#define POE_FID_RDATA 0x152
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#define POE_FID_WDATA 0x153
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#define POE_FID_CMD 0x154
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#define POE_FID_ADDR 0x155
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#define POE_MSG_INFO_CMD 0x156
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#define POE_MSG_INFO_ADDR 0x157
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#define POE_MSG_INFO_RDATA 0x158
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#define POE_LL_CMD 0x159
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#define POE_LL_ADDR 0x15a
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#define POE_LL_RDATA 0x15b
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#define POE_MSG_STG_CMD 0x15c
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#define POE_MSG_STG_ADDR 0x15d
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#define POE_MSG_STG_RDATA 0x15e
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#define POE_DISTR_THRESHOLD_0 0x1c0
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#define POE_DISTR_THRESHOLD_1 0x1c1
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#define POE_DISTR_THRESHOLD_2 0x1c2
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#define POE_DISTR_THRESHOLD_3 0x1c3
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#define POE_DISTR_THRESHOLD_4 0x1c4
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#define POE_DISTR_THRESHOLD(i) (0x1c0 + (i))
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#define POE_DISTR_EN 0x1c5
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#define POE_ENQ_SPILL_THOLD 0x1c8
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#define POE_DEQ_SPILL_THOLD 0x1c9
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#define POE_DEQ_SPILL_TIMER 0x1ca
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#define POE_DISTR_CLASS_DROP_EN 0x1cb
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#define POE_DISTR_VEC_DROP_EN 0x1cc
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#define POE_DISTR_DROP_TIMER 0x1cd
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#define POE_ERROR_LOG_W0 0x1ce
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#define POE_ERROR_LOG_W1 0x1cf
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#define POE_ERROR_LOG_W2 0x1d0
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#define POE_ERR_INJ_CTRL0 0x1d1
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#define POE_TX_TIMER 0x1d4
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#define NUM_DIST_VEC 16
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#define NUM_WORDS_PER_DV 16
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#define MAX_DV_TBL_ENTRIES (NUM_DIST_VEC * NUM_WORDS_PER_DV)
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#define POE_DIST_THRESHOLD_VAL 0xa
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/*
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* POE distribution vectors
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*
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* Each vector is 512 bit with msb indicating vc 512 and lsb indicating vc 0
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* 512-bit-vector is specified as 16 32-bit words.
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* Left most word has the vc range 511-479 right most word has vc range 31 - 0
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* Each word has the MSB select higer vc number and LSB select lower vc num
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*/
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#define POE_DISTVECT_BASE 0x100
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#define POE_DISTVECT(vec) (POE_DISTVECT_BASE + 16 * (vec))
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#define POE_DISTVECT_OFFSET(node,cpu) (4 * (3 - (node)) + (3 - (cpu)/8))
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#define POE_DISTVECT_SHIFT(node,cpu) (((cpu) % 8 ) * 4)
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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#define nlm_read_poe_reg(b, r) nlm_read_reg(b, r)
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#define nlm_write_poe_reg(b, r, v) nlm_write_reg(b, r, v)
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#define nlm_read_poedv_reg(b, r) nlm_read_reg_xkphys(b, r)
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#define nlm_write_poedv_reg(b, r, v) nlm_write_reg_xkphys(b, r, v)
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#define nlm_get_poe_pcibase(node) \
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nlm_pcicfg_base(XLP_IO_POE_OFFSET(node))
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#define nlm_get_poe_regbase(node) \
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(nlm_get_poe_pcibase(node) + XLP_IO_PCI_HDRSZ)
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#define nlm_get_poedv_regbase(node) \
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nlm_xkphys_map_pcibar0(nlm_get_poe_pcibase(node))
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static __inline int
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nlm_poe_max_flows(uint64_t poe_pcibase)
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{
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return (nlm_read_reg(poe_pcibase, XLP_PCI_DEVINFO_REG0));
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}
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/*
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* Helper function, calculate the distribution vector
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* cm0, cm1, cm2, cm3 : CPU masks for nodes 0..3
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* thr_vcmask: destination VCs for a thread
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*/
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static __inline void
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nlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3,
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uint32_t thr_vcmask, uint32_t *distvec)
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{
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uint32_t cpumask = 0, val;
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int i, cpu, node, startcpu, index;
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thr_vcmask &= 0xf;
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for (node = 0; node < XLP_MAX_NODES; node++) {
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switch (node) {
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case 0: cpumask = cm0; break;
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case 1: cpumask = cm1; break;
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case 2: cpumask = cm2; break;
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case 3: cpumask = cm3; break;
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}
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for (i = 0; i < 4; i++) {
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val = 0;
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startcpu = 31 - i * 8;
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for (cpu = startcpu; cpu >= startcpu - 7; cpu--) {
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val <<= 4;
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if (cpumask & (1U << cpu))
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val |= thr_vcmask;
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}
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index = POE_DISTVECT_OFFSET(node, startcpu);
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distvec[index] = val;
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}
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}
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}
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static __inline int
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nlm_write_poe_distvec(uint64_t poedv_base, int vec, uint32_t *distvec)
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{
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uint32_t reg;
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int i;
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if (vec < 0 || vec >= NUM_DIST_VEC)
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return (-1);
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for (i = 0; i < NUM_WORDS_PER_DV; i++) {
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reg = POE_DISTVECT(vec) + i;
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nlm_write_poedv_reg(poedv_base, reg, distvec[i]);
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}
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return (0);
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}
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static __inline void
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nlm_config_poe(uint64_t poe_base, uint64_t poedv_base)
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{
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uint32_t zerodv[NUM_WORDS_PER_DV];
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int i;
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/* First disable distribution vector logic */
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nlm_write_poe_reg(poe_base, POE_DISTR_EN, 0);
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memset(zerodv, 0, sizeof(zerodv));
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for (i = 0; i < NUM_DIST_VEC; i++)
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nlm_write_poe_distvec(poedv_base, i, zerodv);
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/* set the threshold */
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for (i = 0; i < 5; i++)
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nlm_write_poe_reg(poe_base, POE_DISTR_THRESHOLD(i),
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POE_DIST_THRESHOLD_VAL);
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nlm_write_poe_reg(poe_base, POE_DISTR_EN, 1);
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/* always enable local message store */
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nlm_write_poe_reg(poe_base, POE_LOC_ALLOC_EN, 1);
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nlm_write_poe_reg(poe_base, POE_TX_TIMER, 0x3);
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}
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#endif /* !(LOCORE) && !(__ASSEMBLY__) */
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#endif
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