3d69163ace
and R/W emulation aborts under pmap lock.
There were two reasons for using of atomic operations:
(1) the pmap code is based on i386 one where they are used,
(2) there was an idea that access and R/W emulation aborts should be
handled as quick as possible, without pmap locking.
However, the atomic operations in i386 pmap code are used only because
page table entries may be modified by hardware. At the beginning, we
were not sure that it's the only reason. So even if arm hardware does
not modify them, we did not risk to not use them at that time. Further,
it turns out after some testing that using of pmap lock for access and
R/W emulation aborts does not bring any extra cost and there was no
measurable difference. Thus, we have decided finally to use pmap lock
for all operations on page table entries and so, there is no reason for
atomic operations on them. This makes the code cleaner and safer.
This decision introduce a question if it's safe to use pmap lock for
access and R/W emulation aborts. Anyhow, there may happen two cases in
general:
(A) Aborts while the pmap lock is locked already - this should not
happen as pmap lock is not recursive. However, under pmap lock only
internal kernel data should be accessed and such data should be mapped
with A bit set and NM bit cleared. If double abort happens, then
a mapping of data which has caused it must be fixed.
(B) Aborts while another lock(s) is/are locked - this already can
happen. There is no difference here if it's either access or R/W
emulation abort, or if it's some other abort.
Reviewed by: kib
495 lines
9.4 KiB
C
495 lines
9.4 KiB
C
/*-
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* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
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* Copyright 2014 Michal Meloun <meloun@miracle.cz>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PMAP_VAR_H_
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#define _MACHINE_PMAP_VAR_H_
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#include <machine/cpu-v6.h>
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#include <machine/pte-v6.h>
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/*
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* Various PMAP defines, exports, and inline functions
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* definitions also usable in other MD code.
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*/
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/* A number of pages in L1 page table. */
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#define NPG_IN_PT1 (NB_IN_PT1 / PAGE_SIZE)
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/* A number of L2 page tables in a page. */
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#define NPT2_IN_PG (PAGE_SIZE / NB_IN_PT2)
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/* A number of L2 page table entries in a page. */
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#define NPTE2_IN_PG (NPT2_IN_PG * NPTE2_IN_PT2)
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#ifdef _KERNEL
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/*
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* A L2 page tables page contains NPT2_IN_PG L2 page tables. Masking of
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* pte1_idx by PT2PG_MASK gives us an index to associated L2 page table
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* in a page. The PT2PG_SHIFT definition depends on NPT2_IN_PG strictly.
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* I.e., (1 << PT2PG_SHIFT) == NPT2_IN_PG must be fulfilled.
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*/
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#define PT2PG_SHIFT 2
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#define PT2PG_MASK ((1 << PT2PG_SHIFT) - 1)
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/*
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* A PT2TAB holds all allocated L2 page table pages in a pmap.
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* Right shifting of virtual address by PT2TAB_SHIFT gives us an index
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* to L2 page table page in PT2TAB which holds the address mapping.
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*/
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#define PT2TAB_ENTRIES (NPTE1_IN_PT1 / NPT2_IN_PG)
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#define PT2TAB_SHIFT (PTE1_SHIFT + PT2PG_SHIFT)
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/*
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* All allocated L2 page table pages in a pmap are mapped into PT2MAP space.
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* An virtual address right shifting by PT2MAP_SHIFT gives us an index to PTE2
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* which maps the address.
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*/
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#define PT2MAP_SIZE (NPTE1_IN_PT1 * NB_IN_PT2)
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#define PT2MAP_SHIFT PTE2_SHIFT
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extern pt1_entry_t *kern_pt1;
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extern pt2_entry_t *kern_pt2tab;
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extern pt2_entry_t *PT2MAP;
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/*
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* Virtual interface for L1 page table management.
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*/
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static __inline u_int
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pte1_index(vm_offset_t va)
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{
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return (va >> PTE1_SHIFT);
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}
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static __inline pt1_entry_t *
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pte1_ptr(pt1_entry_t *pt1, vm_offset_t va)
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{
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return (pt1 + pte1_index(va));
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}
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static __inline vm_offset_t
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pte1_trunc(vm_offset_t va)
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{
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return (va & PTE1_FRAME);
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}
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static __inline vm_offset_t
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pte1_roundup(vm_offset_t va)
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{
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return ((va + PTE1_OFFSET) & PTE1_FRAME);
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}
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/*
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* Virtual interface for L1 page table entries management.
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*
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* XXX: Some of the following functions now with a synchronization barrier
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* are called in a loop, so it could be useful to have two versions of them.
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* One with the barrier and one without the barrier. In this case, pure
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* barrier pte1_sync() should be implemented as well.
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*/
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static __inline void
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pte1_sync(pt1_entry_t *pte1p)
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{
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dsb();
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#ifndef PMAP_PTE_NOCACHE
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if (!cpuinfo.coherent_walk)
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dcache_wb_pou((vm_offset_t)pte1p, sizeof(*pte1p));
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#endif
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}
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static __inline void
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pte1_sync_range(pt1_entry_t *pte1p, vm_size_t size)
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{
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dsb();
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#ifndef PMAP_PTE_NOCACHE
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if (!cpuinfo.coherent_walk)
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dcache_wb_pou((vm_offset_t)pte1p, size);
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#endif
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}
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static __inline void
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pte1_store(pt1_entry_t *pte1p, pt1_entry_t pte1)
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{
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dmb();
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*pte1p = pte1;
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pte1_sync(pte1p);
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}
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static __inline void
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pte1_clear(pt1_entry_t *pte1p)
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{
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pte1_store(pte1p, 0);
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}
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static __inline void
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pte1_clear_bit(pt1_entry_t *pte1p, uint32_t bit)
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{
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*pte1p &= ~bit;
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pte1_sync(pte1p);
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}
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static __inline boolean_t
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pte1_is_link(pt1_entry_t pte1)
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{
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return ((pte1 & L1_TYPE_MASK) == L1_TYPE_C);
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}
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static __inline int
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pte1_is_section(pt1_entry_t pte1)
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{
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return ((pte1 & L1_TYPE_MASK) == L1_TYPE_S);
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}
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static __inline boolean_t
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pte1_is_dirty(pt1_entry_t pte1)
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{
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return ((pte1 & (PTE1_NM | PTE1_RO)) == 0);
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}
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static __inline boolean_t
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pte1_is_global(pt1_entry_t pte1)
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{
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return ((pte1 & PTE1_NG) == 0);
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}
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static __inline boolean_t
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pte1_is_valid(pt1_entry_t pte1)
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{
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int l1_type;
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l1_type = pte1 & L1_TYPE_MASK;
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return ((l1_type == L1_TYPE_C) || (l1_type == L1_TYPE_S));
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}
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static __inline boolean_t
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pte1_is_wired(pt1_entry_t pte1)
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{
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return (pte1 & PTE1_W);
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}
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static __inline pt1_entry_t
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pte1_load(pt1_entry_t *pte1p)
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{
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pt1_entry_t pte1;
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pte1 = *pte1p;
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return (pte1);
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}
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static __inline pt1_entry_t
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pte1_load_clear(pt1_entry_t *pte1p)
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{
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pt1_entry_t opte1;
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opte1 = *pte1p;
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*pte1p = 0;
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pte1_sync(pte1p);
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return (opte1);
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}
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static __inline void
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pte1_set_bit(pt1_entry_t *pte1p, uint32_t bit)
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{
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*pte1p |= bit;
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pte1_sync(pte1p);
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}
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static __inline vm_paddr_t
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pte1_pa(pt1_entry_t pte1)
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{
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return ((vm_paddr_t)(pte1 & PTE1_FRAME));
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}
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static __inline vm_paddr_t
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pte1_link_pa(pt1_entry_t pte1)
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{
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return ((vm_paddr_t)(pte1 & L1_C_ADDR_MASK));
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}
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/*
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* Virtual interface for L2 page table entries management.
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*
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* XXX: Some of the following functions now with a synchronization barrier
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* are called in a loop, so it could be useful to have two versions of them.
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* One with the barrier and one without the barrier.
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*/
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static __inline void
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pte2_sync(pt2_entry_t *pte2p)
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{
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dsb();
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#ifndef PMAP_PTE_NOCACHE
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if (!cpuinfo.coherent_walk)
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dcache_wb_pou((vm_offset_t)pte2p, sizeof(*pte2p));
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#endif
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}
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static __inline void
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pte2_sync_range(pt2_entry_t *pte2p, vm_size_t size)
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{
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dsb();
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#ifndef PMAP_PTE_NOCACHE
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if (!cpuinfo.coherent_walk)
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dcache_wb_pou((vm_offset_t)pte2p, size);
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#endif
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}
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static __inline void
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pte2_store(pt2_entry_t *pte2p, pt2_entry_t pte2)
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{
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dmb();
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*pte2p = pte2;
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pte2_sync(pte2p);
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}
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static __inline void
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pte2_clear(pt2_entry_t *pte2p)
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{
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pte2_store(pte2p, 0);
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}
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static __inline void
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pte2_clear_bit(pt2_entry_t *pte2p, uint32_t bit)
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{
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*pte2p &= ~bit;
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pte2_sync(pte2p);
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}
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static __inline boolean_t
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pte2_is_dirty(pt2_entry_t pte2)
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{
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return ((pte2 & (PTE2_NM | PTE2_RO)) == 0);
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}
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static __inline boolean_t
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pte2_is_global(pt2_entry_t pte2)
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{
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return ((pte2 & PTE2_NG) == 0);
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}
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static __inline boolean_t
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pte2_is_valid(pt2_entry_t pte2)
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{
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return (pte2 & PTE2_V);
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}
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static __inline boolean_t
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pte2_is_wired(pt2_entry_t pte2)
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{
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return (pte2 & PTE2_W);
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}
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static __inline pt2_entry_t
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pte2_load(pt2_entry_t *pte2p)
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{
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pt2_entry_t pte2;
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pte2 = *pte2p;
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return (pte2);
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}
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static __inline pt2_entry_t
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pte2_load_clear(pt2_entry_t *pte2p)
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{
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pt2_entry_t opte2;
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opte2 = *pte2p;
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*pte2p = 0;
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pte2_sync(pte2p);
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return (opte2);
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}
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static __inline void
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pte2_set_bit(pt2_entry_t *pte2p, uint32_t bit)
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{
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*pte2p |= bit;
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pte2_sync(pte2p);
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}
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static __inline void
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pte2_set_wired(pt2_entry_t *pte2p, boolean_t wired)
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{
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/*
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* Wired bit is transparent for page table walk,
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* so pte2_sync() is not needed.
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*/
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if (wired)
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*pte2p |= PTE2_W;
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else
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*pte2p &= ~PTE2_W;
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}
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static __inline vm_paddr_t
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pte2_pa(pt2_entry_t pte2)
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{
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return ((vm_paddr_t)(pte2 & PTE2_FRAME));
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}
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static __inline u_int
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pte2_attr(pt2_entry_t pte2)
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{
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return ((u_int)(pte2 & PTE2_ATTR_MASK));
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}
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/*
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* Virtual interface for L2 page tables mapping management.
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*/
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static __inline u_int
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pt2tab_index(vm_offset_t va)
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{
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return (va >> PT2TAB_SHIFT);
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}
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static __inline pt2_entry_t *
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pt2tab_entry(pt2_entry_t *pt2tab, vm_offset_t va)
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{
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return (pt2tab + pt2tab_index(va));
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}
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static __inline void
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pt2tab_store(pt2_entry_t *pte2p, pt2_entry_t pte2)
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{
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pte2_store(pte2p,pte2);
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}
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static __inline pt2_entry_t
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pt2tab_load(pt2_entry_t *pte2p)
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{
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return (pte2_load(pte2p));
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}
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static __inline pt2_entry_t
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pt2tab_load_clear(pt2_entry_t *pte2p)
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{
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return (pte2_load_clear(pte2p));
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}
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static __inline u_int
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pt2map_index(vm_offset_t va)
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{
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return (va >> PT2MAP_SHIFT);
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}
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static __inline pt2_entry_t *
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pt2map_entry(vm_offset_t va)
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{
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return (PT2MAP + pt2map_index(va));
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}
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/*
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* Virtual interface for pmap structure & kernel shortcuts.
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*/
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static __inline pt1_entry_t *
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pmap_pte1(pmap_t pmap, vm_offset_t va)
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{
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return (pte1_ptr(pmap->pm_pt1, va));
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}
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static __inline pt1_entry_t *
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kern_pte1(vm_offset_t va)
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{
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return (pte1_ptr(kern_pt1, va));
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}
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static __inline pt2_entry_t *
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pmap_pt2tab_entry(pmap_t pmap, vm_offset_t va)
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{
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return (pt2tab_entry(pmap->pm_pt2tab, va));
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}
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static __inline pt2_entry_t *
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kern_pt2tab_entry(vm_offset_t va)
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{
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return (pt2tab_entry(kern_pt2tab, va));
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}
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static __inline vm_page_t
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pmap_pt2_page(pmap_t pmap, vm_offset_t va)
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{
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pt2_entry_t pte2;
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pte2 = pte2_load(pmap_pt2tab_entry(pmap, va));
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return (PHYS_TO_VM_PAGE(pte2 & PTE2_FRAME));
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}
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static __inline vm_page_t
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kern_pt2_page(vm_offset_t va)
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{
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pt2_entry_t pte2;
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pte2 = pte2_load(kern_pt2tab_entry(va));
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return (PHYS_TO_VM_PAGE(pte2 & PTE2_FRAME));
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}
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#endif /* _KERNEL */
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#endif /* !_MACHINE_PMAP_VAR_H_ */
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