305e7e925f
- Do not use nvf = 4 as it is not really supported by the firmware. Firmwares 1.23.3.0 and above will ignore it silently. - Increase PF4's share of the VIs and let it use all of the RSS table. MFC after: 2 weeks Sponsored by: Chelsio Communications
297 lines
5.9 KiB
Plaintext
297 lines
5.9 KiB
Plaintext
# Firmware configuration file.
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#
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# Global limits (some are hardware limits, others are due to the firmware).
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# nvi = 128 virtual interfaces
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# niqflint = 1023 ingress queues with freelists and/or interrupts
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# nethctrl = 64K Ethernet or ctrl egress queues
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# neq = 64K egress queues of all kinds, including freelists
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# nexactf = 512 MPS TCAM entries, can oversubscribe.
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#
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[global]
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rss_glb_config_mode = basicvirtual
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rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
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# PL_TIMEOUT register
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pl_timeout_value = 10000 # the timeout value in units of us
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# SGE_THROTTLE_CONTROL
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bar2throttlecount = 500 # bar2throttlecount in us
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sge_timer_value = 1, 5, 10, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
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reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if
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# SGE_VFIFO_SIZE is not set, then
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# firmware will set it up in function
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# of number of egress queues used
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reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch
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# threshold set to queue depth
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# minus 128-entries for FL and HP
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# queues, and 0xfff for LP which
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# prompts the firmware to set it up
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# in function of egress queues
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# used
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reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which
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# prompts the firmware to set it up in
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# function of number of egress queues
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# used
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# enable TP_OUT_CONFIG.IPIDSPLITMODE
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reg[0x7d04] = 0x00010000/0x00010000
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# disable TP_PARA_REG3.RxFragEn
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reg[0x7d6c] = 0x00000000/0x00007000
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# enable TP_PARA_REG6.EnableCSnd
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reg[0x7d78] = 0x00000400/0x00000000
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reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
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filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
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filterMask = port, protocol
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tp_pmrx = 20, 512
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tp_pmrx_pagesize = 16K
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# TP number of RX channels (0 = auto)
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tp_nrxch = 0
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tp_pmtx = 40, 512
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tp_pmtx_pagesize = 64K
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# TP number of TX channels (0 = auto)
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tp_ntxch = 0
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# TP OFLD MTUs
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tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
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# TP_GLOBAL_CONFIG
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reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
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# TP_PC_CONFIG
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reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
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# TP_PC_CONFIG2
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reg[0x7d4c] = 0x00010000/0x00010000 # set DisableNewPshFlag
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# TP_PARA_REG0
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reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
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# TP_PARA_REG3
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reg[0x7d6c] = 0x28000000/0x28000000 # set EnableTnlCngHdr
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# set RxMacCheck (Note:
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# Only for hash filter,
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# no tcp offload)
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# TP_PIO_ADDR:TP_RX_LPBK
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reg[tp_pio:0x28] = 0x00208208/0x00ffffff # set commit limits to 8
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# MC configuration
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mc_mode_brc[0] = 0 # mc0 - 1: enable BRC, 0: enable RBC
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mc_mode_brc[1] = 0 # mc1 - 1: enable BRC, 0: enable RBC
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# ULP_TX_CONFIG
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reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ...
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# TPT error.
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# PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
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# these 4 PFs only.
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[function "0"]
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wx_caps = all
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r_caps = all
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nvi = 1
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rssnvi = 0
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x1
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[function "1"]
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wx_caps = all
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r_caps = all
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nvi = 1
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rssnvi = 0
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x2
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[function "2"]
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wx_caps = all
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r_caps = all
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nvi = 1
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rssnvi = 0
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x4
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[function "3"]
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wx_caps = all
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r_caps = all
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nvi = 1
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rssnvi = 0
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x8
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# PF4 is the resource-rich PF that the bus/nexus driver attaches to.
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# It gets 32 MSI/128 MSI-X vectors.
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[function "4"]
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wx_caps = all
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r_caps = all
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nvi = 32
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rssnvi = 16
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niqflint = 512
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nethctrl = 1024
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neq = 2048
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nqpcq = 8192
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nexactf = 456
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cmask = all
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pmask = all
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# driver will mask off features it won't use
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protocol = nic_hashfilter
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tp_l2t = 4096
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# TCAM has 8K cells; each region must start at a multiple of 128 cell.
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# Each entry in these categories takes 4 cells each. nhash will use the
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# TCAM iff there is room left (that is, the rest don't add up to 2048).
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nroute = 32
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nclip = 32
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nfilter = 1008
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nserver = 512
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nhash = 524288
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# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
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# Not used right now.
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[function "5"]
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nvi = 1
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rssnvi = 0
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# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
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# Not used right now.
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[function "6"]
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nvi = 1
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rssnvi = 0
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# The following function, 1023, is not an actual PCIE function but is used to
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# configure and reserve firmware internal resources that come from the global
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# resource pool.
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[function "1023"]
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wx_caps = all
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r_caps = all
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nvi = 4
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rssnvi = 0
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cmask = all
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pmask = all
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nexactf = 8
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nfilter = 16
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# For Virtual functions, we only allow NIC functionality and we only allow
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# access to one port (1 << PF). Note that because of limitations in the
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# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
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# and GTS registers, the number of Ingress and Egress Queues must be a power
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# of 2.
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#
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[function "0/*"]
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wx_caps = 0x82
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r_caps = 0x86
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nvi = 1
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rssnvi = 0
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x1
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[function "1/*"]
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wx_caps = 0x82
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r_caps = 0x86
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nvi = 1
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rssnvi = 0
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x2
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[function "2/*"]
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wx_caps = 0x82
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r_caps = 0x86
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nvi = 1
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rssnvi = 0
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x4
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[function "3/*"]
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wx_caps = 0x82
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r_caps = 0x86
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nvi = 1
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rssnvi = 0
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x8
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# MPS has 192K buffer space for ingress packets from the wire as well as
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# loopback path of the L2 switch.
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[port "0"]
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dcb = none
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bg_mem = 25
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lpbk_mem = 25
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hwm = 30
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lwm = 15
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dwm = 30
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[port "1"]
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dcb = none
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bg_mem = 25
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lpbk_mem = 25
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hwm = 30
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lwm = 15
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dwm = 30
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[port "2"]
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dcb = none
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bg_mem = 25
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lpbk_mem = 25
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hwm = 30
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lwm = 15
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dwm = 30
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[port "3"]
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dcb = none
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bg_mem = 25
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lpbk_mem = 25
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hwm = 30
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lwm = 15
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dwm = 30
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[fini]
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version = 0x1
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checksum = 0x7a962d44
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#
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# $FreeBSD$
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#
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