f173c2b77e
Intelligent NIC driver. The submission conconsists of firmware binary file and driver sources. Submitted by: pkanneganti@cavium.com (Prasad V Kanneganti) Relnotes: Yes Sponsored by: Cavium Networks Differential Revision: https://reviews.freebsd.org/D11927
86 lines
3.2 KiB
C
86 lines
3.2 KiB
C
/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Cavium, Inc.. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Cavium, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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/*
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* \file lio_mem_ops.h
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* \brief Host Driver: Routines used to read/write Octeon memory.
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*/
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#ifndef __LIO_MEM_OPS_H__
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#define __LIO_MEM_OPS_H__
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/*
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* Read a 64-bit value from a BAR1 mapped core memory address.
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* @param oct - pointer to the octeon device.
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* @param core_addr - the address to read from.
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*
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* The range_idx gives the BAR1 index register for the range of address
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* in which core_addr is mapped.
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*
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* @return 64-bit value read from Core memory
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*/
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uint64_t lio_read_device_mem64(struct octeon_device *oct,
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uint64_t core_addr);
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/*
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* Read a 32-bit value from a BAR1 mapped core memory address.
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* @param oct - pointer to the octeon device.
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* @param core_addr - the address to read from.
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*
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* @return 32-bit value read from Core memory
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*/
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uint32_t lio_read_device_mem32(struct octeon_device *oct,
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uint64_t core_addr);
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/*
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* Write a 32-bit value to a BAR1 mapped core memory address.
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* @param oct - pointer to the octeon device.
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* @param core_addr - the address to write to.
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* @param val - 32-bit value to write.
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*/
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void lio_write_device_mem32(struct octeon_device *oct,
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uint64_t core_addr, uint32_t val);
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/* Read multiple bytes from Octeon memory. */
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void lio_pci_read_core_mem(struct octeon_device *oct,
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uint64_t coreaddr, uint8_t *buf,
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uint32_t len);
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/* Write multiple bytes into Octeon memory. */
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void lio_pci_write_core_mem(struct octeon_device *oct,
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uint64_t coreaddr, uint8_t *buf,
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uint32_t len);
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#endif /* __LIO_MEM_OPS_H__ */
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