c3191c2e2b
Background: The coming ibcore update forces an update of mlx4ib(4) which in turn requires an updated mlx4 core module. This also affects the mlx4en(4) module because commonly used APIs are updated. This commit is a middle step updating the mlx4 modules towards the new ibcore. This change contains no major new features. Changes in mlx4: a) Improved error handling when mlx4 PCI devices are detached inside VMs. b) Major update of codebase towards Linux 4.9. Changes in mlx4ib(4): a) Minimal changes needed in order to compile using the updated mlx4 core APIs. Changes in mlx4en(4): a) Update flow steering code in mlx4en to use new APIs for registering MAC addresses and IP addresses. b) Update all statistics counters to be 64-bit. c) Minimal changes needed in order to compile using the updated mlx4 core APIs. Sponsored by: Mellanox Technologies MFC after: 1 week
310 lines
8.3 KiB
C
310 lines
8.3 KiB
C
/*
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* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
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* Copyright (c) 2007, 2008, 2014 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <dev/mlx4/cmd.h>
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#include <dev/mlx4/srq.h>
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#include <linux/module.h>
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#include <linux/gfp.h>
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#include <linux/rcupdate.h>
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#include "mlx4.h"
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#include "icm.h"
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void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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struct mlx4_srq *srq;
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rcu_read_lock();
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srq = radix_tree_lookup(&srq_table->tree, srqn & (dev->caps.num_srqs - 1));
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rcu_read_unlock();
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if (srq)
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atomic_inc(&srq->refcount);
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else {
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mlx4_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
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return;
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}
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srq->event(srq, event_type);
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if (atomic_dec_and_test(&srq->refcount))
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complete(&srq->free);
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}
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static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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int srq_num)
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{
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return mlx4_cmd(dev, mailbox->dma, srq_num, 0,
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MLX4_CMD_SW2HW_SRQ, MLX4_CMD_TIME_CLASS_A,
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MLX4_CMD_WRAPPED);
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}
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static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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int srq_num)
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{
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return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num,
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mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ,
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MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
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}
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static int mlx4_ARM_SRQ(struct mlx4_dev *dev, int srq_num, int limit_watermark)
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{
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return mlx4_cmd(dev, limit_watermark, srq_num, 0, MLX4_CMD_ARM_SRQ,
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MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
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}
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static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
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int srq_num)
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{
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return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ,
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MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
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}
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int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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int err;
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*srqn = mlx4_bitmap_alloc(&srq_table->bitmap);
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if (*srqn == -1)
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return -ENOMEM;
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err = mlx4_table_get(dev, &srq_table->table, *srqn, GFP_KERNEL);
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if (err)
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goto err_out;
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err = mlx4_table_get(dev, &srq_table->cmpt_table, *srqn, GFP_KERNEL);
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if (err)
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goto err_put;
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return 0;
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err_put:
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mlx4_table_put(dev, &srq_table->table, *srqn);
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err_out:
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mlx4_bitmap_free(&srq_table->bitmap, *srqn, MLX4_NO_RR);
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return err;
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}
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static int mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn)
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{
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u64 out_param;
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int err;
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if (mlx4_is_mfunc(dev)) {
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err = mlx4_cmd_imm(dev, 0, &out_param, RES_SRQ,
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RES_OP_RESERVE_AND_MAP,
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MLX4_CMD_ALLOC_RES,
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MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
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if (!err)
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*srqn = get_param_l(&out_param);
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return err;
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}
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return __mlx4_srq_alloc_icm(dev, srqn);
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}
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void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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mlx4_table_put(dev, &srq_table->cmpt_table, srqn);
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mlx4_table_put(dev, &srq_table->table, srqn);
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mlx4_bitmap_free(&srq_table->bitmap, srqn, MLX4_NO_RR);
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}
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static void mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn)
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{
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u64 in_param = 0;
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if (mlx4_is_mfunc(dev)) {
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set_param_l(&in_param, srqn);
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if (mlx4_cmd(dev, in_param, RES_SRQ, RES_OP_RESERVE_AND_MAP,
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MLX4_CMD_FREE_RES,
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MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
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mlx4_warn(dev, "Failed freeing cq:%d\n", srqn);
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return;
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}
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__mlx4_srq_free_icm(dev, srqn);
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}
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int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd,
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struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_srq_context *srq_context;
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u64 mtt_addr;
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int err;
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err = mlx4_srq_alloc_icm(dev, &srq->srqn);
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if (err)
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return err;
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spin_lock_irq(&srq_table->lock);
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err = radix_tree_insert(&srq_table->tree, srq->srqn, srq);
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spin_unlock_irq(&srq_table->lock);
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if (err)
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goto err_icm;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox)) {
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err = PTR_ERR(mailbox);
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goto err_radix;
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}
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srq_context = mailbox->buf;
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srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) |
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srq->srqn);
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srq_context->logstride = srq->wqe_shift - 4;
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srq_context->xrcd = cpu_to_be16(xrcd);
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srq_context->pg_offset_cqn = cpu_to_be32(cqn & 0xffffff);
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srq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
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mtt_addr = mlx4_mtt_addr(dev, mtt);
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srq_context->mtt_base_addr_h = mtt_addr >> 32;
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srq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
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srq_context->pd = cpu_to_be32(pdn);
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srq_context->db_rec_addr = cpu_to_be64(db_rec);
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err = mlx4_SW2HW_SRQ(dev, mailbox, srq->srqn);
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mlx4_free_cmd_mailbox(dev, mailbox);
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if (err)
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goto err_radix;
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atomic_set(&srq->refcount, 1);
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init_completion(&srq->free);
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return 0;
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err_radix:
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spin_lock_irq(&srq_table->lock);
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radix_tree_delete(&srq_table->tree, srq->srqn);
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spin_unlock_irq(&srq_table->lock);
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err_icm:
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mlx4_srq_free_icm(dev, srq->srqn);
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return err;
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}
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EXPORT_SYMBOL_GPL(mlx4_srq_alloc);
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void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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int err;
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err = mlx4_HW2SW_SRQ(dev, NULL, srq->srqn);
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if (err)
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mlx4_warn(dev, "HW2SW_SRQ failed (%d) for SRQN %06x\n", err, srq->srqn);
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spin_lock_irq(&srq_table->lock);
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radix_tree_delete(&srq_table->tree, srq->srqn);
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spin_unlock_irq(&srq_table->lock);
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if (atomic_dec_and_test(&srq->refcount))
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complete(&srq->free);
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wait_for_completion(&srq->free);
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mlx4_srq_free_icm(dev, srq->srqn);
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}
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EXPORT_SYMBOL_GPL(mlx4_srq_free);
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int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark)
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{
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return mlx4_ARM_SRQ(dev, srq->srqn, limit_watermark);
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}
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EXPORT_SYMBOL_GPL(mlx4_srq_arm);
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int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark)
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{
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struct mlx4_cmd_mailbox *mailbox;
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struct mlx4_srq_context *srq_context;
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int err;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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srq_context = mailbox->buf;
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err = mlx4_QUERY_SRQ(dev, mailbox, srq->srqn);
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if (err)
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goto err_out;
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*limit_watermark = be16_to_cpu(srq_context->limit_watermark);
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err_out:
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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EXPORT_SYMBOL_GPL(mlx4_srq_query);
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int mlx4_init_srq_table(struct mlx4_dev *dev)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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int err;
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spin_lock_init(&srq_table->lock);
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INIT_RADIX_TREE(&srq_table->tree, GFP_ATOMIC);
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if (mlx4_is_slave(dev))
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return 0;
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err = mlx4_bitmap_init(&srq_table->bitmap, dev->caps.num_srqs,
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dev->caps.num_srqs - 1, dev->caps.reserved_srqs, 0);
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if (err)
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return err;
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return 0;
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}
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void mlx4_cleanup_srq_table(struct mlx4_dev *dev)
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{
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if (mlx4_is_slave(dev))
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return;
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mlx4_bitmap_cleanup(&mlx4_priv(dev)->srq_table.bitmap);
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}
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struct mlx4_srq *mlx4_srq_lookup(struct mlx4_dev *dev, u32 srqn)
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{
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struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table;
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struct mlx4_srq *srq;
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rcu_read_lock();
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srq = radix_tree_lookup(&srq_table->tree,
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srqn & (dev->caps.num_srqs - 1));
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rcu_read_unlock();
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return srq;
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}
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EXPORT_SYMBOL_GPL(mlx4_srq_lookup);
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