217ec20885
Added support for LLDP passthru Upgrade ECORE to version 8.33.5.0 Upgrade STORMFW to version 8.33.7.0 Added support for SRIOV MFC after:5 days
215 lines
10 KiB
C
215 lines
10 KiB
C
/*
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* Copyright (c) 2017-2018 Cavium, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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/****************************************************************************
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* Name: spad_layout.h
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*
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* Description: Global definitions
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*
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* Created: 01/09/2013
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*
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****************************************************************************/
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/*
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* Spad Layout NVM CFG MCP public
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*==========================================================================================================
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* MCP_REG_SCRATCH REG_RD(MISC_REG_GEN_PURP_CR0) REG_RD(MISC_REG_SHARED_MEM_ADDR)
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* +------------------+ +-------------------------+ +-------------------+
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* | Num Sections(4B)|Currently 4 | Num Sections(4B) | | Num Sections(4B)|Currently 6
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* +------------------+ +-------------------------+ +-------------------+
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* | Offsize(Trace) |4B -+ +-- | Offset(NVM_CFG1) | | Offsize(drv_mb) |
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* +-| Offsize(NVM_CFG) |4B | | | (Size is fixed) | | Offsize(mfw_mb) |
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*+-|-| Offsize(Public) |4B | +-> +-------------------------+ | Offsize(global) |
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*| | | Offsize(Private) |4B | | | | Offsize(path) |
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*| | +------------------+ <--+ | nvm_cfg1_glob | | Offsize(port) |
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*| | | | +-------------------------+ | Offsize(func) |
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*| | | Trace | | nvm_cfg1_path 0 | +-------------------+
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*| +>+------------------+ | nvm_cfg1_path 1 | | drv_mb PF0/2/4..|8 Funcs of engine0
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*| | | +-------------------------+ | drv_mb PF1/3/5..|8 Funcs of engine1
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*| | NVM_CFG | | nvm_cfg1_port 0 | +-------------------+
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*+-> +------------------+ | .... | | mfw_mb PF0/2/4..|8 Funcs of engine0
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* | | | nvm_cfg1_port 3 | | mfw_mb PF1/3/5..|8 Funcs of engine1
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* | Public Data | +-------------------------+ +-------------------+
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* +------------------+ 8 Funcs of Engine 0| nvm_cfg1_func PF0/2/4/..| | |
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* | | 8 Funcs of Engine 1| nvm_cfg1_func PF1/3/5/..| | public_global |
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* | Private Data | +-------------------------+ +-------------------+
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* +------------------+ | public_path 0 |
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* | Code | | public_path 1 |
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* | Static Area | +-------------------+
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* +--- ---+ | public_port 0 |
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* | Code | | .... |
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* | PIM Area | | public_port 3 |
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* +------------------+ +-------------------+
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* | public_func 0/2/4.|8 Funcs of engine0
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* | public_func 1/3/5.|8 Funcs of engine1
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* +-------------------+
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*/
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#ifndef SPAD_LAYOUT_H
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#define SPAD_LAYOUT_H
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#ifndef MDUMP_PARSE_TOOL
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#define PORT_0 0
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#define PORT_1 1
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#define PORT_2 2
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#define PORT_3 3
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#include "mcp_public.h"
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#include "mfw_hsi.h"
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#include "nvm_cfg.h"
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#ifdef MFW
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#include "mcp_private.h"
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#endif
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extern struct spad_layout g_spad;
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/* TBD - Consider renaming to MCP_STATIC_SPAD_SIZE, since the real size includes another 64kb */
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#define MCP_SPAD_SIZE 0x00028000 /* 160 KB */
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#define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
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#endif /* MDUMP_PARSE_TOOL */
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#define TO_OFFSIZE(_offset, _size) \
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(u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_OFFSET) | \
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(((u32)(_size) >> 2) << OFFSIZE_SIZE_OFFSET))
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enum spad_sections {
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SPAD_SECTION_TRACE,
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SPAD_SECTION_NVM_CFG,
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SPAD_SECTION_PUBLIC,
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SPAD_SECTION_PRIVATE,
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SPAD_SECTION_MAX /* Cannot be modified anymore since ROM relying on this size !! */
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};
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#ifndef MDUMP_PARSE_TOOL
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struct spad_layout {
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struct nvm_cfg nvm_cfg;
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struct mcp_public_data public_data;
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#ifdef MFW /* Drivers will not be compiled with this flag. */
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/* Linux should remove this appearance at all. */
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struct mcp_private_data private_data;
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#endif
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};
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#endif /* MDUMP_PARSE_TOOL */
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#define STRUCT_OFFSET(f) (STATIC_INIT_BASE + __builtin_offsetof(struct static_init, f))
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/* This section is located at a fixed location in the beginning of the scratchpad,
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* to ensure that the MCP trace is not run over during MFW upgrade.
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* All the rest of data has a floating location which differs from version to version,
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* and is pointed by the mcp_meta_data below.
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* Moreover, the spad_layout section is part of the MFW firmware, and is loaded with it
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* from nvram in order to clear this portion.
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*/
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struct static_init {
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u32 num_sections; /* 0xe20000 */
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offsize_t sections[SPAD_SECTION_MAX]; /* 0xe20004 */
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#define SECTION(_sec_) *((offsize_t*)(STRUCT_OFFSET(sections[_sec_])))
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#ifdef SECURE_BOOT
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u32 tim_sha256[8]; /* Used by E5 ROM. Do not relocate */
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u32 rom_status_code; /* Used by E5 ROM. Do not relocate */
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u32 secure_running_mfw; /* Instead of the one after the trace_buffer */ /* Used by E5 ROM. Do not relocate */
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#define SECURE_RUNNING_MFW *((u32*)(STRUCT_OFFSET(secure_running_mfw)))
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#endif
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struct mcp_trace trace; /* 0xe20014 */
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#ifdef MFW
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#define MCP_TRACE_P ((struct mcp_trace*)(STRUCT_OFFSET(trace)))
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u8 trace_buffer[MCP_TRACE_SIZE]; /* 0xe20030 */
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#define MCP_TRACE_BUF ((u8*)(STRUCT_OFFSET(trace_buffer)))
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/* running_mfw has the same definition as in nvm_map.h.
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* This bit indicate both the running dir, and the running bundle.
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* It is set once when the LIM is loaded.
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*/
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u32 running_mfw; /* 0xe20830 */
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#define RUNNING_MFW *((u32*)(STRUCT_OFFSET(running_mfw)))
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u32 build_time; /* 0xe20834 */
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#define MFW_BUILD_TIME *((u32*)(STRUCT_OFFSET(build_time)))
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u32 reset_type; /* 0xe20838 */
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#define RESET_TYPE *((u32*)(STRUCT_OFFSET(reset_type)))
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u32 mfw_secure_mode; /* 0xe2083c */
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#define MFW_SECURE_MODE *((u32*)(STRUCT_OFFSET(mfw_secure_mode)))
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u16 pme_status_pf_bitmap; /* 0xe20840 */
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#define PME_STATUS_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_status_pf_bitmap)))
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u16 pme_enable_pf_bitmap;
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#define PME_ENABLE_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_enable_pf_bitmap)))
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u32 mim_nvm_addr; /* 0xe20844 */
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u32 mim_start_addr; /* 0xe20848 */
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u32 ah_pcie_link_params; /* 0xe20850 Stores PCIe link configuration at start, so they can be used later also for Hot-Reset, without the need to re-reading them from nvm cfg. */
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#define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
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#define AH_PCIE_LINK_PARAMS_LINK_SPEED_OFFSET (0)
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#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
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#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_OFFSET (8)
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#define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
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#define AH_PCIE_LINK_PARAMS_ASPM_MODE_OFFSET (16)
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#define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
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#define AH_PCIE_LINK_PARAMS_ASPM_CAP_OFFSET (24)
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#define AH_PCIE_LINK_PARAMS *((u32*)(STRUCT_OFFSET(ah_pcie_link_params)))
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u32 flags; /* 0xe20850 */
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#define M_GLOB_FLAGS *((u32*)(STRUCT_OFFSET(flags)))
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#define FLAGS_VAUX_REQUIRED (1 << 0)
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#define FLAGS_WAIT_AVS_READY (1 << 1)
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#define FLAGS_FAILURE_ISSUED (1 << 2)
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#define FLAGS_FAILURE_DETECTED (1 << 3)
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#define FLAGS_VAUX (1 << 4)
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#define FLAGS_PERST_ASSERT_OCCURED (1 << 5)
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#define FLAGS_HOT_RESET_STEP2 (1 << 6)
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#define FLAGS_MSIX_SYNC_ALLOWED (1 << 7)
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#define FLAGS_PROGRAM_PCI_COMPLETED (1 << 8)
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#define FLAGS_SMBUS_AUX_MODE (1 << 9)
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#define FLAGS_PEND_SMBUS_VMAIN_TO_AUX (1 << 10)
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#define FLAGS_NVM_CFG_EFUSE_FAILURE (1 << 11)
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#define FLAGS_POWER_TRANSITION (1 << 12)
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#define FLAGS_MCTP_CHECK_PUMA_TIMEOUT (1 << 13)
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#define FLAGS_MCTP_TX_PLDM_UPDATE (1 << 14)
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#define FLAGS_MCTP_SENSOR_EVENT (1 << 15)
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#define FLAGS_PMBUS_ERROR (1 << 28)
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#define FLAGS_OS_DRV_LOADED (1 << 29)
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#define FLAGS_OVER_TEMP_OCCUR (1 << 30)
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#define FLAGS_FAN_FAIL_OCCUR (1 << 31)
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u32 rsrv_persist[4]; /* Persist reserved for MFW upgrades */ /* 0xe20854 */
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#endif /* MFW */
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};
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#ifndef MDUMP_PARSE_TOOL
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#define NVM_CFG1(x) g_spad.nvm_cfg.cfg1.x
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#define NVM_GLOB(x) NVM_CFG1(glob).x
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#define NVM_GLOB_VAL(n, m, o) ((NVM_GLOB(n) & m) >> o)
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#endif /* MDUMP_PARSE_TOOL */
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#endif /* SPAD_LAYOUT_H */
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