718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
280 lines
11 KiB
C
280 lines
11 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2012
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* Ben Gray <bgray@freebsd.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_SMSCREG_H_
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#define _IF_SMSCREG_H_
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/*
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* Definitions for the SMSC LAN9514 and LAN9514 USB to ethernet controllers.
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*
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* This information was gleaned from the SMSC driver in the linux kernel, where
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* it is Copyrighted (C) 2007-2008 SMSC.
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*
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*/
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/**
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* TRANSMIT FRAMES
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* ---------------
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* Tx frames are prefixed with an 8-byte header which describes the frame
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*
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* 4 bytes 4 bytes variable
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* +------------+------------+--- . . . . . . . . . . . . ---+
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* | TX_CTRL_0 | TX_CTRL_1 | Ethernet frame data |
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* +------------+------------+--- . . . . . . . . . . . . ---+
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*
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* Where the headers have the following fields:
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*
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* TX_CTRL_0 <20:16> Data offset
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* TX_CTRL_0 <13> First segment of frame indicator
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* TX_CTRL_0 <12> Last segment of frame indicator
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* TX_CTRL_0 <10:0> Buffer size (?)
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*
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* TX_CTRL_1 <14> Perform H/W checksuming on IP packets
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* TX_CTRL_1 <13> Disable automatic ethernet CRC generation
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* TX_CTRL_1 <12> Disable padding (?)
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* TX_CTRL_1 <10:0> Packet byte length
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*
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*/
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#define SMSC_TX_CTRL_0_OFFSET(x) (((x) & 0x1FUL) << 16)
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#define SMSC_TX_CTRL_0_FIRST_SEG (0x1UL << 13)
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#define SMSC_TX_CTRL_0_LAST_SEG (0x1UL << 12)
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#define SMSC_TX_CTRL_0_BUF_SIZE(x) ((x) & 0x000007FFUL)
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#define SMSC_TX_CTRL_1_CSUM_ENABLE (0x1UL << 14)
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#define SMSC_TX_CTRL_1_CRC_DISABLE (0x1UL << 13)
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#define SMSC_TX_CTRL_1_PADDING_DISABLE (0x1UL << 12)
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#define SMSC_TX_CTRL_1_PKT_LENGTH(x) ((x) & 0x000007FFUL)
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/**
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* RECEIVE FRAMES
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* --------------
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* Rx frames are prefixed with an 4-byte status header which describes any
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* errors with the frame as well as things like the length
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*
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* 4 bytes variable
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* +------------+--- . . . . . . . . . . . . ---+
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* | RX_STAT | Ethernet frame data |
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* +------------+--- . . . . . . . . . . . . ---+
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*
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* Where the status header has the following fields:
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*
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* RX_STAT <30> Filter Fail
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* RX_STAT <29:16> Frame Length
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* RX_STAT <15> Error Summary
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* RX_STAT <13> Broadcast Frame
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* RX_STAT <12> Length Error
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* RX_STAT <11> Runt Frame
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* RX_STAT <10> Multicast Frame
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* RX_STAT <7> Frame too long
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* RX_STAT <6> Collision Seen
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* RX_STAT <5> Frame Type
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* RX_STAT <4> Receive Watchdog
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* RX_STAT <3> Mii Error
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* RX_STAT <2> Dribbling
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* RX_STAT <1> CRC Error
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*
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*/
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#define SMSC_RX_STAT_FILTER_FAIL (0x1UL << 30)
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#define SMSC_RX_STAT_FRM_LENGTH(x) (((x) >> 16) & 0x3FFFUL)
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#define SMSC_RX_STAT_ERROR (0x1UL << 15)
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#define SMSC_RX_STAT_BROADCAST (0x1UL << 13)
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#define SMSC_RX_STAT_LENGTH_ERROR (0x1UL << 12)
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#define SMSC_RX_STAT_RUNT (0x1UL << 11)
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#define SMSC_RX_STAT_MULTICAST (0x1UL << 10)
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#define SMSC_RX_STAT_FRM_TO_LONG (0x1UL << 7)
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#define SMSC_RX_STAT_COLLISION (0x1UL << 6)
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#define SMSC_RX_STAT_FRM_TYPE (0x1UL << 5)
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#define SMSC_RX_STAT_WATCHDOG (0x1UL << 4)
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#define SMSC_RX_STAT_MII_ERROR (0x1UL << 3)
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#define SMSC_RX_STAT_DRIBBLING (0x1UL << 2)
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#define SMSC_RX_STAT_CRC_ERROR (0x1UL << 1)
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/**
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* REGISTERS
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*
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*/
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#define SMSC_ID_REV 0x000
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#define SMSC_INTR_STATUS 0x008
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#define SMSC_RX_CFG 0x00C
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#define SMSC_TX_CFG 0x010
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#define SMSC_HW_CFG 0x014
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#define SMSC_PM_CTRL 0x020
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#define SMSC_LED_GPIO_CFG 0x024
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#define SMSC_GPIO_CFG 0x028
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#define SMSC_AFC_CFG 0x02C
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#define SMSC_EEPROM_CMD 0x030
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#define SMSC_EEPROM_DATA 0x034
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#define SMSC_BURST_CAP 0x038
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#define SMSC_GPIO_WAKE 0x064
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#define SMSC_INTR_CFG 0x068
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#define SMSC_BULK_IN_DLY 0x06C
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#define SMSC_MAC_CSR 0x100
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#define SMSC_MAC_ADDRH 0x104
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#define SMSC_MAC_ADDRL 0x108
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#define SMSC_HASHH 0x10C
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#define SMSC_HASHL 0x110
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#define SMSC_MII_ADDR 0x114
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#define SMSC_MII_DATA 0x118
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#define SMSC_FLOW 0x11C
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#define SMSC_VLAN1 0x120
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#define SMSC_VLAN2 0x124
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#define SMSC_WUFF 0x128
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#define SMSC_WUCSR 0x12C
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#define SMSC_COE_CTRL 0x130
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/* ID / Revision register */
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#define SMSC_ID_REV_CHIP_ID_MASK 0xFFFF0000UL
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#define SMSC_ID_REV_CHIP_REV_MASK 0x0000FFFFUL
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#define SMSC_RX_FIFO_FLUSH (0x1UL << 0)
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#define SMSC_TX_CFG_ON (0x1UL << 2)
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#define SMSC_TX_CFG_STOP (0x1UL << 1)
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#define SMSC_TX_CFG_FIFO_FLUSH (0x1UL << 0)
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#define SMSC_HW_CFG_BIR (0x1UL << 12)
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#define SMSC_HW_CFG_LEDB (0x1UL << 11)
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#define SMSC_HW_CFG_RXDOFF (0x3UL << 9) /* RX pkt alignment */
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#define SMSC_HW_CFG_DRP (0x1UL << 6)
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#define SMSC_HW_CFG_MEF (0x1UL << 5)
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#define SMSC_HW_CFG_LRST (0x1UL << 3) /* Lite reset */
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#define SMSC_HW_CFG_PSEL (0x1UL << 2)
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#define SMSC_HW_CFG_BCE (0x1UL << 1)
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#define SMSC_HW_CFG_SRST (0x1UL << 0)
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#define SMSC_PM_CTRL_PHY_RST (0x1UL << 4) /* PHY reset */
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#define SMSC_LED_GPIO_CFG_SPD_LED (0x1UL << 24)
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#define SMSC_LED_GPIO_CFG_LNK_LED (0x1UL << 20)
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#define SMSC_LED_GPIO_CFG_FDX_LED (0x1UL << 16)
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/* Hi watermark = 15.5Kb (~10 mtu pkts) */
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/* low watermark = 3k (~2 mtu pkts) */
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/* backpressure duration = ~ 350us */
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/* Apply FC on any frame. */
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#define AFC_CFG_DEFAULT (0x00F830A1)
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#define SMSC_EEPROM_CMD_BUSY (0x1UL << 31)
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#define SMSC_EEPROM_CMD_MASK (0x7UL << 28)
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#define SMSC_EEPROM_CMD_READ (0x0UL << 28)
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#define SMSC_EEPROM_CMD_WRITE (0x3UL << 28)
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#define SMSC_EEPROM_CMD_ERASE (0x5UL << 28)
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#define SMSC_EEPROM_CMD_RELOAD (0x7UL << 28)
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#define SMSC_EEPROM_CMD_TIMEOUT (0x1UL << 10)
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#define SMSC_EEPROM_CMD_ADDR_MASK 0x000001FFUL
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/* MAC Control and Status Register */
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#define SMSC_MAC_CSR_RCVOWN (0x1UL << 23) /* Half duplex */
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#define SMSC_MAC_CSR_LOOPBK (0x1UL << 21) /* Loopback */
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#define SMSC_MAC_CSR_FDPX (0x1UL << 20) /* Full duplex */
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#define SMSC_MAC_CSR_MCPAS (0x1UL << 19) /* Multicast mode */
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#define SMSC_MAC_CSR_PRMS (0x1UL << 18) /* Promiscuous mode */
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#define SMSC_MAC_CSR_INVFILT (0x1UL << 17) /* Inverse filtering */
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#define SMSC_MAC_CSR_PASSBAD (0x1UL << 16) /* Pass on bad frames */
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#define SMSC_MAC_CSR_HPFILT (0x1UL << 13) /* Hash filtering */
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#define SMSC_MAC_CSR_BCAST (0x1UL << 11) /* Broadcast */
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#define SMSC_MAC_CSR_TXEN (0x1UL << 3) /* TX enable */
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#define SMSC_MAC_CSR_RXEN (0x1UL << 2) /* RX enable */
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/* Interrupt control register */
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#define SMSC_INTR_NTEP (0x1UL << 31)
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#define SMSC_INTR_MACRTO (0x1UL << 19)
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#define SMSC_INTR_TX_STOP (0x1UL << 17)
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#define SMSC_INTR_RX_STOP (0x1UL << 16)
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#define SMSC_INTR_PHY_INT (0x1UL << 15)
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#define SMSC_INTR_TXE (0x1UL << 14)
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#define SMSC_INTR_TDFU (0x1UL << 13)
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#define SMSC_INTR_TDFO (0x1UL << 12)
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#define SMSC_INTR_RXDF (0x1UL << 11)
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#define SMSC_INTR_GPIOS 0x000007FFUL
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/* Phy MII interface register */
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#define SMSC_MII_WRITE (0x1UL << 1)
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#define SMSC_MII_READ (0x0UL << 1)
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#define SMSC_MII_BUSY (0x1UL << 0)
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/* H/W checksum register */
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#define SMSC_COE_CTRL_TX_EN (0x1UL << 16) /* Tx H/W csum enable */
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#define SMSC_COE_CTRL_RX_MODE (0x1UL << 1)
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#define SMSC_COE_CTRL_RX_EN (0x1UL << 0) /* Rx H/W csum enable */
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/* Registers on the phy, accessed via MII/MDIO */
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#define SMSC_PHY_INTR_STAT (29)
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#define SMSC_PHY_INTR_MASK (30)
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#define SMSC_PHY_INTR_ENERGY_ON (0x1U << 7)
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#define SMSC_PHY_INTR_ANEG_COMP (0x1U << 6)
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#define SMSC_PHY_INTR_REMOTE_FAULT (0x1U << 5)
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#define SMSC_PHY_INTR_LINK_DOWN (0x1U << 4)
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/* USB Vendor Requests */
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#define SMSC_UR_WRITE_REG 0xA0
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#define SMSC_UR_READ_REG 0xA1
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#define SMSC_UR_GET_STATS 0xA2
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#define SMSC_CONFIG_INDEX 0 /* config number 1 */
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#define SMSC_IFACE_IDX 0
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/*
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* USB endpoints.
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*/
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enum {
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SMSC_BULK_DT_RD,
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SMSC_BULK_DT_WR,
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/* the LAN9514 device does support interrupt endpoints, however I couldn't
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* get then to work reliably and since they are unneeded (poll the mii
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* status) they are unused.
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* SMSC_INTR_DT_WR,
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* SMSC_INTR_DT_RD,
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*/
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SMSC_N_TRANSFER,
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};
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struct smsc_softc {
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struct usb_ether sc_ue;
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struct mtx sc_mtx;
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struct usb_xfer *sc_xfer[SMSC_N_TRANSFER];
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int sc_phyno;
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/* The following stores the settings in the mac control (MAC_CSR) register */
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uint32_t sc_mac_csr;
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uint32_t sc_rev_id;
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uint32_t sc_flags;
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#define SMSC_FLAG_LINK 0x0001
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#define SMSC_FLAG_LAN9514 0x1000 /* LAN9514 */
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};
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#define SMSC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define SMSC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define SMSC_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
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#endif /* _IF_SMSCREG_H_ */
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