2668945977
now uave a full copy of the arm device tree sources to help when adding support for newer boards. Sponsored by: ABT Systems Ltd
366 lines
9.0 KiB
Plaintext
366 lines
9.0 KiB
Plaintext
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "imx6ul.dtsi"
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/ {
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model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
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compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
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chosen {
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stdout-path = &uart1;
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};
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memory {
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reg = <0x80000000 0x20000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_sd1_vmmc: sd1_regulator {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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};
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&cpu0 {
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arm-supply = <®_arm>;
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soc-supply = <®_soc>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@2 {
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reg = <2>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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flash0: n25q256a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a";
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spi-max-frequency = <29000000>;
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reg = <0>;
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};
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};
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&snvs_poweroff {
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status = "okay";
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};
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&tsc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc>;
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xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
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measure-delay-time = <0xffff>;
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pre-charge-time = <0xfff>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
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keep-power-in-suspend;
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enable-sdio-wakeup;
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vmmc-supply = <®_sd1_vmmc>;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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no-1-8-v;
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keep-power-in-suspend;
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enable-sdio-wakeup;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_csi1: csi1grp {
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fsl,pins = <
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MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
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MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
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MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
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MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
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MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
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MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
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MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
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MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
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MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
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MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
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MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
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MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
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MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059
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>;
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};
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pinctrl_flexcan1: flexcan1grp{
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fsl,pins = <
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MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
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MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
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>;
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};
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pinctrl_flexcan2: flexcan2grp{
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fsl,pins = <
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MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
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MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
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MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
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>;
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};
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pinctrl_lcdif_dat: lcdifdatgrp {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
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MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
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MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
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MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
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MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
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MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
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MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
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MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
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MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
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MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
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MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
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MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
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MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
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MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
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MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
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MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
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MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
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MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
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MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
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MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
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MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
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MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
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MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
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MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
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>;
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};
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pinctrl_lcdif_ctrl: lcdifctrlgrp {
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fsl,pins = <
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MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
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MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
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MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
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MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
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/* used for lcd reset */
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MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
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MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
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MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
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MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
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MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
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MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
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>;
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};
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pinctrl_pwm1: pwm1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
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>;
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};
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pinctrl_sim2: sim2grp {
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fsl,pins = <
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MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
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MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
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MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
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MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
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MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
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MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
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>;
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};
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pinctrl_tsc: tscgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
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MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
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MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
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MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
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MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
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MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
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MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
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MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
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MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
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MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
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MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
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MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
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MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
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MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
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MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
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>;
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};
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};
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