586b0ae5aa
Linux ath9k. The ath9k ar9002_hw_init_cal() isn't entirely clear about what is supposed to be called for what chipsets, so I'm ignoring the rest of it and just porting the AR9285 init cal path as-is and leaving the rest alone. Subsequent commits may also tidy up the Merlin (AR9285) and other chipset support. Obtained from: Linux ath9k
270 lines
9.0 KiB
C
270 lines
9.0 KiB
C
/*
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* Copyright (c) 2008-2010 Atheros Communications Inc.
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* Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_eeprom_v4k.h"
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#include "ar9002/ar9285.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#include "ar9002/ar9002phy.h"
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#include "ar9002/ar9285phy.h"
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#include "ar9002/ar9285_cal.h"
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#define AR9285_CLCAL_REDO_THRESH 1
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#define MAX_PACAL_SKIPCOUNT 8
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#define N(a) (sizeof (a) / sizeof (a[0]))
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static void
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ar9285_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)
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{
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uint32_t regVal;
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int i, offset, offs_6_1, offs_0;
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uint32_t ccomp_org, reg_field;
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uint32_t regList[][2] = {
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{ 0x786c, 0 },
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{ 0x7854, 0 },
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{ 0x7820, 0 },
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{ 0x7824, 0 },
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{ 0x7868, 0 },
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{ 0x783c, 0 },
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{ 0x7838, 0 },
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};
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HALDEBUG(ah, HAL_DEBUG_PERCAL, "Running PA Calibration\n");
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/* PA CAL is not needed for high power solution */
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if (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL) ==
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AR5416_EEP_TXGAIN_HIGH_POWER)
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return;
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for (i = 0; i < N(regList); i++)
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regList[i][1] = OS_REG_READ(ah, regList[i][0]);
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regVal = OS_REG_READ(ah, 0x7834);
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regVal &= (~(0x1));
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OS_REG_WRITE(ah, 0x7834, regVal);
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regVal = OS_REG_READ(ah, 0x9808);
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regVal |= (0x1 << 27);
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OS_REG_WRITE(ah, 0x9808, regVal);
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OS_REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
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ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
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OS_REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
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OS_DELAY(30);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
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for (i = 6; i > 0; i--) {
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regVal = OS_REG_READ(ah, 0x7834);
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regVal |= (1 << (19 + i));
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OS_REG_WRITE(ah, 0x7834, regVal);
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OS_DELAY(1);
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regVal = OS_REG_READ(ah, 0x7834);
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regVal &= (~(0x1 << (19 + i)));
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reg_field = MS(OS_REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
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regVal |= (reg_field << (19 + i));
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OS_REG_WRITE(ah, 0x7834, regVal);
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}
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
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OS_DELAY(1);
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reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
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offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
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offs_0 = MS(OS_REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
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offset = (offs_6_1<<1) | offs_0;
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offset = offset - 0;
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offs_6_1 = offset>>1;
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offs_0 = offset & 1;
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if ((!is_reset) && (AH9285(ah)->pacal_info.prev_offset == offset)) {
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if (AH9285(ah)->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
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AH9285(ah)->pacal_info.max_skipcount =
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2 * AH9285(ah)->pacal_info.max_skipcount;
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AH9285(ah)->pacal_info.skipcount = AH9285(ah)->pacal_info.max_skipcount;
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} else {
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AH9285(ah)->pacal_info.max_skipcount = 1;
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AH9285(ah)->pacal_info.skipcount = 0;
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AH9285(ah)->pacal_info.prev_offset = offset;
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}
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
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regVal = OS_REG_READ(ah, 0x7834);
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regVal |= 0x1;
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OS_REG_WRITE(ah, 0x7834, regVal);
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regVal = OS_REG_READ(ah, 0x9808);
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regVal &= (~(0x1 << 27));
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OS_REG_WRITE(ah, 0x9808, regVal);
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for (i = 0; i < N(regList); i++)
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OS_REG_WRITE(ah, regList[i][0], regList[i][1]);
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OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
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}
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void
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ar9002_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset)
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{
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if (AR_SREV_KITE_12_OR_LATER(ah)) {
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if (is_reset || !AH9285(ah)->pacal_info.skipcount)
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ar9285_hw_pa_cal(ah, is_reset);
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else
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AH9285(ah)->pacal_info.skipcount--;
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}
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}
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/* Carrier leakage Calibration fix */
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static HAL_BOOL
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ar9285_hw_cl_cal(struct ath_hal *ah, const struct ieee80211_channel *chan)
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{
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OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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if (IEEE80211_IS_CHAN_HT20(chan)) {
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OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
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OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
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OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_FLTR_CAL);
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OS_REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
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OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
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if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
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AR_PHY_AGC_CONTROL_CAL, 0)) {
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HALDEBUG(ah, HAL_DEBUG_PERCAL,
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"offset calibration failed to complete in 1ms; noisy environment?\n");
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return AH_FALSE;
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}
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OS_REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
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OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
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OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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}
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OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
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OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
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if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
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0)) {
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HALDEBUG(ah, HAL_DEBUG_PERCAL,
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"offset calibration failed to complete in 1ms; noisy environment?\n");
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return AH_FALSE;
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}
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OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
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OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
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return AH_TRUE;
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}
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static HAL_BOOL
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ar9285_hw_clc(struct ath_hal *ah, const struct ieee80211_channel *chan)
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{
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int i;
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uint32_t txgain_max;
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uint32_t clc_gain, gain_mask = 0, clc_num = 0;
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uint32_t reg_clc_I0, reg_clc_Q0;
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uint32_t i0_num = 0;
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uint32_t q0_num = 0;
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uint32_t total_num = 0;
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uint32_t reg_rf2g5_org;
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HAL_BOOL retv = AH_TRUE;
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if (!(ar9285_hw_cl_cal(ah, chan)))
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return AH_FALSE;
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txgain_max = MS(OS_REG_READ(ah, AR_PHY_TX_PWRCTRL7),
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AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
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for (i = 0; i < (txgain_max+1); i++) {
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clc_gain = (OS_REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
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AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
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if (!(gain_mask & (1 << clc_gain))) {
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gain_mask |= (1 << clc_gain);
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clc_num++;
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}
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}
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for (i = 0; i < clc_num; i++) {
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reg_clc_I0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
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& AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
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reg_clc_Q0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
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& AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
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if (reg_clc_I0 == 0)
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i0_num++;
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if (reg_clc_Q0 == 0)
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q0_num++;
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}
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total_num = i0_num + q0_num;
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if (total_num > AR9285_CLCAL_REDO_THRESH) {
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reg_rf2g5_org = OS_REG_READ(ah, AR9285_RF2G5);
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if (AR_SREV_9285E_20(ah)) {
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OS_REG_WRITE(ah, AR9285_RF2G5,
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(reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
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AR9285_RF2G5_IC50TX_XE_SET);
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} else {
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OS_REG_WRITE(ah, AR9285_RF2G5,
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(reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
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AR9285_RF2G5_IC50TX_SET);
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}
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retv = ar9285_hw_cl_cal(ah, chan);
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OS_REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
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}
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return retv;
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}
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HAL_BOOL
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ar9285InitCalHardware(struct ath_hal *ah,
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const struct ieee80211_channel *chan)
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{
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if (! ar9285_hw_clc(ah, chan))
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return AH_FALSE;
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ar9285_hw_pa_cal(ah, AH_TRUE);
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return AH_TRUE;
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}
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