252 lines
11 KiB
C
252 lines
11 KiB
C
/******************************************************************************
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Copyright (c) 2001-2010, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _E1000_ICH8LAN_H_
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#define _E1000_ICH8LAN_H_
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#define ICH_FLASH_GFPREG 0x0000
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#define ICH_FLASH_HSFSTS 0x0004
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#define ICH_FLASH_HSFCTL 0x0006
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#define ICH_FLASH_FADDR 0x0008
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#define ICH_FLASH_FDATA0 0x0010
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/* Requires up to 10 seconds when MNG might be accessing part. */
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#define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
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#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
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#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
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#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
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#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
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#define ICH_CYCLE_READ 0
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#define ICH_CYCLE_WRITE 2
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#define ICH_CYCLE_ERASE 3
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#define FLASH_GFPREG_BASE_MASK 0x1FFF
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#define FLASH_SECTOR_ADDR_SHIFT 12
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#define ICH_FLASH_SEG_SIZE_256 256
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#define ICH_FLASH_SEG_SIZE_4K 4096
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#define ICH_FLASH_SEG_SIZE_8K 8192
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#define ICH_FLASH_SEG_SIZE_64K 65536
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#define ICH_FLASH_SECTOR_SIZE 4096
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#define ICH_FLASH_REG_MAPSIZE 0x00A0
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#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
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#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
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/* FW established a valid mode */
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#define E1000_ICH_FWSM_FW_VALID 0x00008000
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#define E1000_ICH_MNG_IAMT_MODE 0x2
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#define E1000_FWSM_PROXY_MODE 0x00000008 /* FW is in proxy mode */
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/* Shared Receive Address Registers */
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#define E1000_SHRAL(_i) (0x05438 + ((_i) * 8))
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#define E1000_SHRAH(_i) (0x0543C + ((_i) * 8))
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#define E1000_SHRAH_AV 0x80000000 /* Addr Valid bit */
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#define E1000_SHRAH_MAV 0x40000000 /* Multicast Addr Valid bit */
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#define E1000_H2ME 0x05B50 /* Host to ME */
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#define E1000_H2ME_LSECREQ 0x00000001 /* Linksec Request */
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#define E1000_H2ME_LSECA 0x00000002 /* Linksec Active */
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#define E1000_H2ME_LSECSF 0x00000004 /* Linksec Failed */
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#define E1000_H2ME_LSECD 0x00000008 /* Linksec Disabled */
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#define E1000_H2ME_SLCAPD 0x00000010 /* Start LCAPD */
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#define E1000_H2ME_IPV4_ARP_EN 0x00000020 /* Arp Offload enable bit */
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#define E1000_H2ME_IPV6_NS_EN 0x00000040 /* NS Offload enable bit */
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#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
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(ID_LED_OFF1_OFF2 << 8) | \
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(ID_LED_OFF1_ON2 << 4) | \
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(ID_LED_DEF1_DEF2))
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#define E1000_ICH_NVM_SIG_WORD 0x13
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#define E1000_ICH_NVM_SIG_MASK 0xC000
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#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
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#define E1000_ICH_NVM_SIG_VALUE 0x80
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#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
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#define E1000_FEXTNVM_SW_CONFIG 1
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#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
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#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
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#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
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#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
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#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
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#define E1000_ICH_RAR_ENTRIES 7
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#define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
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#define PHY_PAGE_SHIFT 5
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#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
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((reg) & MAX_PHY_REG_ADDRESS))
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#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
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#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
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#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
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#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
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#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
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#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
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#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
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#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
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/* PHY Wakeup Registers and defines */
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#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
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#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
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#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
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#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
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#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
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#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
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#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
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#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
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#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
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#define BM_IPAV (BM_PHY_REG(BM_WUC_PAGE, 64))
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#define BM_IP4AT_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2)))
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#define BM_IP4AT_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2)))
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#define BM_SHRAL_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4)))
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#define BM_SHRAL_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4)))
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#define BM_SHRAH_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4)))
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#define BM_SHRAH_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4)))
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#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
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#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
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#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
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#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
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#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
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#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
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#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
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#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
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#define HV_MUX_DATA_CTRL PHY_REG(776, 16)
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#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
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#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
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#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
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#define HV_SCC_LOWER PHY_REG(778, 17)
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#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
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#define HV_ECOL_LOWER PHY_REG(778, 19)
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#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
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#define HV_MCC_LOWER PHY_REG(778, 21)
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#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */
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#define HV_LATECOL_LOWER PHY_REG(778, 24)
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#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */
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#define HV_COLC_LOWER PHY_REG(778, 26)
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#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */
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#define HV_DC_LOWER PHY_REG(778, 28)
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#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
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#define HV_TNCRS_LOWER PHY_REG(778, 30)
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#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
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#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
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#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
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/* SMBus Address Phy Register */
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#define HV_SMB_ADDR PHY_REG(768, 26)
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#define HV_SMB_ADDR_MASK 0x007F
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#define HV_SMB_ADDR_PEC_EN 0x0200
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#define HV_SMB_ADDR_VALID 0x0080
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/* Strapping Option Register - RO */
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#define E1000_STRAP 0x0000C
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#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
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#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
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/* OEM Bits Phy Register */
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#define HV_OEM_BITS PHY_REG(768, 25)
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#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
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#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
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#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
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#define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy address bit from LCD Config word */
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/* KMRN Mode Control */
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#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
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#define HV_KMRN_MDIO_SLOW 0x0400
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/* PHY Power Management Control */
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#define HV_PM_CTRL PHY_REG(770, 17)
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#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
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/* PHY Low Power Idle Control */
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#define I82579_LPI_CTRL PHY_REG(772, 20)
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#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
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/* EMI Registers */
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#define I82579_EMI_ADDR 0x10
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#define I82579_EMI_DATA 0x11
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#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
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/*
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* Additional interrupts need to be handled for ICH family:
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* DSW = The FW changed the status of the DISSW bit in FWSM
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* PHYINT = The LAN connected device generates an interrupt
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* EPRST = Manageability reset event
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*/
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#define IMS_ICH_ENABLE_MASK (\
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E1000_IMS_DSW | \
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E1000_IMS_PHYINT | \
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E1000_IMS_EPRST)
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/* Additional interrupt register bit definitions */
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#define E1000_ICR_LSECPNC 0x00004000 /* PN threshold - client */
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#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
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#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC /* PN threshold - client */
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/* Security Processing bit Indication */
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#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000
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#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000
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#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000
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#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
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#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000
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/* Receive Address Initial CRC Calculation */
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#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
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void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
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bool state);
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void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
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void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
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void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw);
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s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
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s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config);
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s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
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void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
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s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
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#endif
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